Semiconductor package, manufacturing method thereof and IC chip

Abstract

A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire. The bump land and the wire land may be spaced apart from each other on an active surface of the IC chip.

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         12 . A method comprising:
 providing a first circuit substrate strip including a plurality of unit packages;   separating individual unit packages from the first circuit substrate strip;   providing the individual unit packages on a second circuit substrate strip to provide a plurality of stack structures;   providing a molding resin on the stack structures on the second circuit substrate strip; and   separating individual stack packages from the second circuit substrate strip.   
     
     
         13 . The method of  claim 12 , further comprising:
 preparing the first circuit substrate strip including a plurality of circuit substrates;   providing wire bonding pads on a lower surface of each of the circuit substrates;   providing chip bonding pads on an upper surface of each of the circuit substrates;   providing IC chips on the lower surfaces of the circuit substrates, each IC chip having an active surface supporting wire lands and chip bumps; and   connecting the wire bonding pads to the wire lands using bonding wires.   
     
     
         14 . The method of  claim 13 , wherein providing stack structures comprises:
 providing a first unit package on the second circuit substrate; and   providing a second unit package on the first unit package,   the chip bumps of the second unit package being connected to the chip bonding pads of the first unit package.   
     
     
         15 . The method of  claim 12 , further comprising forming a plurality of solder bumps on the second circuit substrate. 
     
     
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         19 . A method comprising:
 providing an upper unit package and a lower unit package, each including
 a circuit substrate supporting chip bonding pads, and 
 an IC chip provided on the circuit substrate, the IC chip having an active surface with bump lands; and 
   providing chip bumps on the bump lands of the upper unit package;   connecting the chip bumps of the upper unit package to the chip bonding pads of the lower unit package.   
     
     
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