Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time

Abstract

Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.

1 - 13 . (canceled) 
     
     
         14 . A non-volatile semiconductor memory device, comprising:
 a normal memory cell array;   a spare memory cell array;   a normal decode circuit selecting a portion of said normal memory cell array in accordance with an address signal;   a redundancy determination circuit performing redundancy determination upon receiving said address signal;   a gate circuit forcibly activating an output from said redundancy determination circuit in response to a test signal; and   a spare decode circuit selecting a portion of said spare memory cell array in accordance with an output from said gate circuit and said address signal wherein   said spare decode circuit selects a specific portion of said spare memory cell array once in a plurality of times when said address signal is incremented at activation of said test signal.   
     
     
         15 . The non-volatile semiconductor memory device according to  claim 14 , wherein
 at activation of said test signal, a probability of selection of a specific memory transistor in said spare memory cell array is equal to a probability of selection of a specific memory transistor in said normal memory cell array when said address signal is incremented in a prescribed range.