Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods

Abstract

An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

1 . A method of making a stacked semiconductor assembly comprising:
 providing a first semiconductor die having an active surface bearing integrated circuitry and a back surface, the first semiconductor die defining at least one via having a substantially uniform cross-section extending from the active surface to the back surface with conductive material filling the at least one via;   forming at least one electrically conductive redistribution line on the back surface of the first semiconductor die in electrical communication with the conductive material in the at least one via and extending to a location on the back surface of the first semiconductor die remote from the location of the at least one via;   attaching a second semiconductor die to the first semiconductor die, the second semiconductor die having an active surface, a back surface, and at least one via therethrough extending from the active surface to the back surface thereof; and   electrically connecting the back surface of the first semiconductor die to the active surface of the second semiconductor die so that at least one conductive element on the active surface of the second semiconductor die is electrically connected to the at least one redistribution line at the location on the back surface of the first semiconductor die.   
     
     
         2 . The method of  claim 1 , wherein providing comprises:
 forming the at least one via in the active surface of the first semiconductor die to extend partially through the first semiconductor die;   filling the at least one via with the conductive material; and   removing material from the back surface of the first semiconductor die to expose the conductive material in the at least one via.   
     
     
         3 . The method of  claim 2 , wherein forming the at least one via comprises at least one of drilling and laser ablation. 
     
     
         4 . The method of  claim 2 , wherein filling comprises depositing conductive material over the active surface to fill the at least one via. 
     
     
         5 . The method of  claim 2 , wherein removing comprises:
 grinding material from the back surface of the first semiconductor die; and   applying at least one of a wet etch and a dry etch on the back surface to expose the conductive material on the back surface.   
     
     
         6 . The method of  claim 2 , wherein removing comprises abrasively removing. 
     
     
         7 . The method of  claim 2 , wherein removing comprises:
 grinding the material from the back surface of the first semiconductor die; and   abrasively polishing the back surface to expose the conductive material on the back surface and to planarize the back surface.   
     
     
         8 . The method of  claim 1 , wherein disposing the conductive material comprises doping a matrix material of the first semiconductor die to simultaneously define the at least one via and render it conductive. 
     
     
         9 . The method of  claim 1 , wherein forming comprises:
 depositing a redistribution layer precursor on the back surface of the first semiconductor die; and   patterning the redistribution layer to define the at least one redistribution line on the back surface.   
     
     
         10 . The method of  claim 9 , wherein patterning comprises selectively masking and etching the redistribution layer precursor to remove excess material of the redistribution layer precursor to form the at least one redistribution line on the back surface. 
     
     
         11 . The method of  claim 1 , wherein forming comprises printing the at least one redistribution line on the back surface. 
     
     
         12 . The method of  claim 1 , wherein forming comprises applying the at least one redistribution line as a preform to the back surface. 
     
     
         13 . The method of  claim 1 , wherein forming comprises positioning a conductive bump on a portion of the at least one redistribution line proximate the location on the back surface.