US2008153205A1PendingUtilityA1

Semiconductor device and a method for manufacturing the same

Assignee: NISHIZAWA HIROTAKAPriority: Mar 11, 2005Filed: Feb 26, 2008Published: Jun 26, 2008
Est. expiryMar 11, 2025(expired)· nominal 20-yr term from priority
H10W 72/5522H10W 74/00H10W 72/0198A47G 25/50A47G 25/20G06K 19/07732H05K 1/145H10W 90/401H10W 70/699
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Claims

Abstract

A semiconductor device comprising a first wiring board having a plurality of external connection terminals on one side, semiconductor chips mounted on the other side of the first wiring board and electrically connected to the first wiring board by a plurality of wires, a sealing resin for sealing the semiconductor chips and the wires, and a second wiring board having a plurality of contact points on one side and bonded to the top surface of the sealing resin on the other side, wherein the upper end portions of the loops of the plurality of wires for electrically connecting the first wiring board to the semiconductor chips are exposed from the top surface of the sealing resin and electrically connected to the second wiring board.

Claims

exact text as granted — not AI-modified
1 - 7 . (canceled) 
   
   
       8 . A method for manufacturing a semiconductor device, comprising the steps of:
 (a) preparing a first wiring board having a plurality of external connection terminals on one side and a second wiring board having a plurality of contact points on one side;   (b) mounting semiconductor chips over the other side of the first wiring board and electrically connecting the first wiring board to the semiconductor chips by wires;   (c) placing the first wiring board in a mold in such a manner that the other side faces up and bringing the upper end portions of the loops of the wires into contact with the top of the cavity of the mold;   (d) injecting a resin into the cavity to seal the semiconductor chips and the wires with the sealing resin and exposing the upper end portions of the loops of the wires from the top surface of the sealing resin; and   (e) bonding the other side of the second wiring board to the top surface of the sealing resin to electrically connect the wires exposed from the top surface of the sealing resin to the second wiring board.   
   
   
       9 . The method for manufacturing a semiconductor device according to  claim 8 , further comprising a step of applying a conductive adhesive to the wires exposed from the top surface of the sealing resin after the step (d) and before the step (e). 
   
   
       10 . The method for manufacturing a semiconductor device according to  claim 8 , further comprising a step of removing flush burrs which adhere to the wires exposed from the top surface of the sealing resin after the step (d) and before the step (e). 
   
   
       11 . The method for manufacturing a semiconductor device according to  claim 10 , wherein the flush burrs are removed by laser sputtering the top surface of the sealing resin. 
   
   
       12 . The method for manufacturing a semiconductor device according to  claim 8 , further comprising a step of cutting the first wiring board, the second wiring board and the sealing resin after the step (e). 
   
   
       13 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the first wiring board, the second wiring board and the sealing resin are cut by a water jet system. 
   
   
       14 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the first wiring board, the second wiring board and the sealing resin are cut by a water jet system and a dicing system. 
   
   
       15 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the first wiring board, the second wiring board and the sealing resin after the cutting step have outside dimensions based on Mini-UICC standards. 
   
   
       16 . The method for manufacturing a semiconductor device according to  claim 8 , wherein the semiconductor chips include:
 a first semiconductor chip having an electrically erasable and writable non-volatile memory;   a second semiconductor chip having an interface controller for controlling memory interface operation for the non-volatile memory; and   a third semiconductor chip having an IC card microcomputer for carrying out processing based on an operation command given from the interface controller, and the upper end portions of the loops of the plurality of wires for electrically connecting the first wiring board to the third semiconductor chip are exposed from the top surface of the sealing resin and electrically connected to the second wiring board.   
   
   
       17 - 21 . (canceled)

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