System and method for memory element characterization

Abstract

A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.

1 . A latch design system, comprising:
 a modeling module configured to model a latch using a simulation method;   a simulation module configured to determine component response characteristics for components of the latch and compute safety regions in a state space of the latch, the safety regions indicating stable states for the latch; and   a transient analysis module configured to determine transient responses for the latch in an open state to geometrically determine a path and time needed to reach one of the safety regions, the path and the time being used to determine a clock waveform for placing a corresponding state in the one of the safety regions.   
   
   
       2 . The system as recited in  claim 1 , wherein the transient analysis module determines set and hold times for the latch based upon a clock waveform by employing the bounds determined for the safety region. 
   
   
       3 . The system as recited in  claim 1 , wherein the simulation method includes equations. 
   
   
       4 . The system as recited in  claim 1 , wherein modeling the memory element using a simulation method includes modeling the memory element using simulation software. 
   
   
       5 . The system as recited in  claim 1 , wherein the path and the time needed to reach one of the safety regions is determined based on a geometric layout of the state space. 
   
   
       6 . The system as recited in  claim 1 , wherein the safety regions are based on simulation experiments performed on the latch. 
   
   
       7 . A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
 a modeling module configured to model a latch using a simulation method;   a simulation module configured to determine component response characteristics for components of the latch and compute safety regions in a state space of the latch, the safety regions indicating stable states for the latch; and   a transient analysis module configured to determine transient responses for the latch in an open state to geometrically determine a path and time needed to reach one of the safety regions, the path and the time being used to determine a clock waveform for placing a corresponding state in the one of the safety regions.   
   
   
       8 . The design structure as recited in  claim 7 , wherein the transient analysis module determines set and hold times for the latch based upon a clock waveform by employing the bounds determined for the safety region. 
   
   
       9 . The design structure as recited in  claim 7 , wherein the simulation method includes equations. 
   
   
       10 . The design structure as recited in  claim 7 , wherein modeling the memory element using a simulation method includes modeling the memory element using simulation software. 
   
   
       11 . The design structure as recited in  claim 7 , wherein the path and the time needed to reach one of the safety regions is determined based on a geometric layout of the state space. 
   
   
       12 . The design structure as recited in  claim 7 , wherein the safety regions are based on simulation experiments performed on the latch.