Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same

Abstract

A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

1 . A stack package comprising:
 an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are formed in the upper semiconductor chip under the respective first bonding pads; and   a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.   
   
   
       2 . The stack package according to  claim 1 , wherein the via-hole and the bump have the same cross-sectional shape. 
   
   
       3 . The stack package according to  claim 2 , wherein the via-hole and the bump have the cross-sectional shape of a trapezoid. 
   
   
       4 . The stack package according to  claim 1 , wherein the lower semiconductor chip includes an insulation layer which is formed on the upper surface of the lower semiconductor chip so as to expose the second bonding pads. 
   
   
       5 . The stack package according to  claim 1 , further comprising:
 a bonding material interposed between the upper and lower semiconductor chips.   
   
   
       6 . The stack package according to  claim 1 , wherein the bumps are made of metal. 
   
   
       7 . The stack package according to  claim 6 , wherein the bumps are formed of aluminum or copper. 
   
   
       8 . The stack package according to  claim 6 , wherein the bumps include a metal seed layer formed at the interface with the second bonding pads. 
   
   
       9 . The stack package according to  claim 8  , wherein the metal seed layer is formed of aluminum or copper. 
   
   
       10 . A method of manufacturing a stack package, comprising the steps of:
 forming a first mask pattern on a lower surface of a first semiconductor chip having a plurality of first bonding pads formed on an upper surface thereof, wherein the first mask pattern exposes portions of the lower surface of the first semiconductor chip corresponding to the respective locations of the first bonding pads formed on the upper surface;   etching the exposed portions of the lower surface of the first semiconductor chip to expose the respective first bonding pads so as to define via holes;   constituting an upper semiconductor chip by removing the first mask pattern from the lower surface of the first semiconductor chip   forming an insulation layer on an upper surface of a second semiconductor chip having a plurality of second bonding pads formed on the upper surface thereof in the same manner as the first semiconductor chip, wherein the insulation layer are formed to expose the second bonding pads;   forming a metal seed layer on the exposed second bonding pads and the insulation layer;   forming a second mask pattern on the metal seed layer wherein the second mask pattern has openings to expose the upper regions of the second bonding pads;   forming bumps by plating a metal layer to fill the openings of the second mask pattern such that the bumps are formed on the portions of the metal seed layer exposed through the openings of the second mask pattern;   constituting an lower semiconductor chip by removing the second mask pattern and any portions of the metal seed layer outside the openings of the second mask pattern of the second semiconductor chip; and   attaching the lower semiconductor chip to the lower surface of the upper semiconductor chip such that the bumps of the lower semiconductor chip are inserted into the respective via-holes and are come into the respective first bonding pads.   
   
   
       11 . The method according to  claim 10 , wherein all of the steps recited in  claim 10  including the step of forming the first mask pattern to the step of attaching the lower and upper semiconductor chips are implemented at a wafer-level. 
   
   
       12 . The method according to  claim 11  further comprises the step of:
 cutting the upper and lower semiconductor chips attached to each other at the wafer-level into a chip-level after performing the step of attaching the lower semiconductor chip to the upper semiconductor chip.   
   
   
       13 . The method according to  claim 10 , wherein the second mask pattern is formed to have the openings having a trapezoidal cross-sectional shape. 
   
   
       14 . The method according to  claim 10 , wherein the via-holes and the bumps have a same trapezoidal cross-sectional shape. 
   
   
       15 . The method according to  claim 10 , wherein the step of defining the via-holes is implemented using the first bonding pads as an etch stop layer. 
   
   
       16 . The method according to  claim 10 , wherein the upper and lower semiconductor chips are attached to each other by utilizing a medium of bonding material. 
   
   
       17 . The method according to  claim 10 , wherein the bonding pads of the upper semiconductor chip and the metal bumps of the lower semiconductor chip are attached to each other through a heat-pressing process. 
   
   
       18 . The method according to  claim 10 , wherein the bumps are formed of aluminum or copper. 
   
   
       19 . The method according to  claim 10 , wherein the metal seed layer is formed of aluminum or copper.