Parallel read for front end compression mode

Abstract

Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of data lines required for transmitting compressed test data. Data lines effectively freed up due to compression of test data read from one bank may be used to carry test data for another bank.

1 . A memory device, comprising:
 a plurality of banks of memory cells;   one or more test logic circuits, each configured to generate, from a plurality of bits read from a bank, a reduced number of one or more compressed test data bits; and   logic configured to route a plurality of bits from multiple banks of the memory device to the test logic circuits in parallel, route the compressed test data bits from each bank to a common set of data lines shared between the multiple banks, and provide the compressed test data bits as output on one or more data pins of the memory device, wherein the plurality of banks comprises at least two groups of memory banks, with banks in each group sharing a first common set of data lines and the groups sharing a second set of common data lines; and   the one or more test logic circuits comprise a test logic circuit for each group of memory banks.   
   
   
       2 . The memory device of  claim 1 , wherein the test logic for each group of memory banks generates a reduced number of test data bits from data received on the first common set of data lines and routes the reduced number of compressed data bits to the second set of common data lines. 
   
   
       3 . The memory device of  claim 1 , wherein the plurality of banks comprises more than four banks. 
   
   
       4 . The memory device of  claim 1 , wherein the logic is configured to output the plurality of compressed data bits on one or more data pins on successive clock cycle edges. 
   
   
       5 . A memory device, comprising:
 multiple banks of memory cells;   test means for generating, from a plurality of bits read from a bank, a reduced number of one or more compressed test data bits; and   control means configured to, when the device is in a test mode, route a plurality of bits from multiple banks of the memory device to the test means in parallel, route the compressed test data bits from each bank to a first set of common data lines shared between the groups, and provide the compressed test data bits as output on one or more data pins of the memory device,   wherein the plurality of banks comprises at least two groups of memory banks, with banks in each group sharing a first common set of data lines and the groups sharing a second set of common data lines; and   wherein separate test means are provided for each group of memory banks.   
   
   
       6 . The memory device of  claim 5 , wherein the test means for each group of banks generates a reduced number of test data bits from data received on the first common set of data lines and routes the reduced number of compressed data bits to the second set of common data lines. 
   
   
       7 . The memory device of  claim 5 , wherein the plurality of banks comprises more than four banks.