Semiconductor package, manufacturing method thereof and IC chip

Abstract

A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire. The bump land and the wire land may be spaced apart from each other on an active surface of the IC chip.

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         21 . A package comprising:
 an unit package including
 a circuit substrate core having chip bonding pads formed directly on a surface thereof, 
 an IC chip provided on the circuit substrate, the IC chip having bump lands, and 
 chip bumps provided on the bump lands; 
   a second circuit substrate including   an upper surface supporting chip bonding pads and a lower surface supporting external connection terminal pads, the chip bumps of the unit package being connected to the chip bonding pads of the second circuit substrate.   
     
     
         22 . The package of  claim 21 , wherein the circuit substrate core has a lower surface and an upper surface, each of the lower surface and the upper surface having a solder mask thereon. 
     
     
         23 . The package of  claim 21 , further comprising:
 a bonding wire electrically connects the circuit substrate to the IC chip.   
     
     
         24 . The package of  claim 21 , further comprising:
 solder balls formed on the external connection terminal pads of the second circuit substrate.   
     
     
         25 . The package of  claim 21 , further comprising:
 a molding resin provided in the unit package.   
     
     
         26 . The package of  claim 21 , further comprising:
 an underfill resin provided in the unit package.   
     
     
         27 . The package of  claim 21 , wherein the substrate core has at least one layer of a dielectric material and at least one conductive layer. 
     
     
         28 . The package of  claim 21 , wherein the unit package includes an adhesive layer provided between the IC chip and the lower surface of the circuit substrate. 
     
     
         29 . The package of  claim 28 , wherein the adhesive layer includes one of a liquid adhesive and an adhesive sheet. 
     
     
         30 . The package of  claim 23 , wherein the IC chip includes wire lands and the substrate core includes wire bonding pads, wherein connecting portions of the bonding wires at the wire lands and the wire bonding pads are one of a ball-ball type, a ball-wedge type, a wedge-ball type and a wedge-wedge type. 
     
     
         31 . The package of  claim 23 , wherein the bonding wires have heights that are less than that of the chip bumps relative to the active surface of the IC chip. 
     
     
         32 . The package of  claim 21 , wherein the IC chip further comprises:
 a substrate;   a conductive layer provided on the substrate, the conductive layer defining a bump land for supporting a chip bump and a wire land for connecting to a bonding wire, the bump land and the wire land being spaced apart from each other on the surface of the IC chip.   
     
     
         33 . The package of  claim 22 , wherein the bonding wire is connected between the wire land of the IC chip and the wire bonding pad of the substrate. 
     
     
         34 . A package comprising;
 an upper unit package and a lower unit package, each including
 a circuit substrate core having chip bonding pads formed directly on a surface thereof, 
 an IC chip provided on the circuit substrate, the IC chip having bump lands, and 
   chip bumps provided on the bump lands;   a second circuit substrate including   an upper surface supporting chip bonding pads and a lower surface supporting external connection terminal pads, the chip bumps of the upper unit package being connected to the chip bonding pads of the lower unit package and the chip bumps of the lower unit package being connected to the chip bonding pads of the second circuit substrate.   
     
     
         35 . The package of  claim 34 , wherein each of the unit packages includes a bonding wire electrically connecting the circuit substrate to the IC chip. 
     
     
         36 . The package of  claim 34 , further comprising:
 solder balls formed on the external connection terminal pads of the second circuit substrate.   
     
     
         37 . The package of  claim 34 , further comprising:
 a molding resin provided in each of the lower and the upper unit packages.   
     
     
         38 . The package of  claim 34 , further comprising:
 an underfill resin provided in each of the lower and the upper unit packages.   
     
     
         39 . The package of  claim 34 , wherein the substrate core has at least one layer of a dielectric material and at least one conductive layer. 
     
     
         40 . The package of  claim 34 , wherein the lower and the upper unit packages includes an adhesive layer provided between the IC chip and the lower surface of the circuit substrate. 
     
     
         41 . The package of  claim 40 , wherein the adhesive layer includes one of a liquid adhesive and an adhesive sheet. 
     
     
         42 . The package of  claim 35 , wherein the IC chip includes wire lands and the substrate core includes wire bonding pads, wherein connecting portions of the bonding wires at the wire lands and the wire bonding pads are one of a ball-ball type, a ball-wedge type, a wedge-ball type and a wedge-wedge type. 
     
     
         43 . The package of  claim 35 , wherein the bonding wires have heights that are less than that of the chip bumps relative to the active surface of the IC chip. 
     
     
         44 . The package of  claim 34 , wherein the IC chip further comprises:
 a substrate;   a conductive layer provided on the substrate, the conductive layer defining a bump land for supporting a chip bump and a wire land for connecting to a bonding wire, the bump land and the wire land being spaced apart from each other on the surface of the IC chip.   
     
     
         45 . The package of  claim 44 , wherein the bonding wire is connected between the wire land of the IC chip and the wire bonding pad of the substrate. 
     
     
         46 . The package of  claim 34 , wherein at least one of the circuit substrate core further comprises:
 a lower surface and an upper surface, each of the lower surface and the upper surface having a solder mask thereon.