Method for forming STI of semiconductor device

Abstract

A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

1 - 3 . (canceled) 
   
   
       4 . A method for forming a shallow trench isolation (STI) of a semiconductor device, comprising:
 forming a trench by removing selected portions of a pad nitride film and a pad oxide film and a portion of a semiconductor substrate underlying the pad oxide film;   forming a voltage characteristic anomaly attenuating structure by selectively growing an epitaxial silicon layer on a surface of the trench so as to have a rounded edge at a top portion adjacent to an opening edge of the trench;   forming a liner oxide layer on the epitaxial silicon layer; and   filling a void within the liner oxide layer with an oxide material.   
   
   
       5 . The method of  claim 4 , further comprising performing a CMP (Chemical Mechanical Polishing) process on an upper surface of the oxide material filled into the void to form the STI. 
   
   
       6 . A shallow trench isolation formed using a method, comprising: preparing a semiconductor substrate having an active region and a field region defined thereon;
 forming, in succession, a pad oxide film and a pad nitride film on the semiconductor substrate by selectively etching the pad oxide film, the nitride film and the semiconductor substrate on the field region, to form a trench;   selectively growing an epitaxial silicon layer on a surface of the trench, including forming a rounded edge at a top portion of said epitaxial silicon layer adjacent to a top opening edge of said trench;   forming a liner oxide layer on the epitaxial silicon layer; and   forming a STI in the trench.   
   
   
       7 . A shallow trench isolation formed using a method, comprising:
 forming, in succession, a pad oxide film and a pad nitride film on a semiconductor substrate having an active region and a field region defined therein;   selectively removing portions of the pad oxide film, the nitride film and the semiconductor substrate on the field region to form a trench;   selectively growing an epitaxial silicon layer on a surface of the trench, including forming a rounded edge at a top portion of said epitaxial silicon layer adjacent to a top opening edge of said trench; and   forming a liner oxide layer on the epitaxial silicon layer; and   forming a STI in the trench.   
   
   
       8 . A shallow trench isolation formed using the method of  claim 4 . 
   
   
       9 . A shallow trench isolation formed using the method of  claim 5 . 
   
   
       10 . A shallow trench isolation (STI) of a semiconductor device, comprising:
 a trench structure extending through a pad nitride film, a pad oxide film and into an underlying portion of a semiconductor substrate;   an epitaxial silicon layer on a surface of the trench;   a voltage characteristic anomaly attenuating structure comprising a rounded edge on a top portion of the epitaxial silicon layer adjacent to an opening edge of the trench;   a liner oxide layer on the epitaxial silicon layer; and   an oxide material filing the void within the linear oxide layer and pad nitride film.   
   
   
       11 . A shallow trench isolation (STI) of a semiconductor device, comprising:
 a trench structure extending through a pad nitride film, a pad oxide film and into an underlying portion of a semiconductor substrate;   an epitaxial silicon layer on a surface of the trench;   means for attenuating a voltage characteristic anomaly associated with the epitaxial silicon layer;   a liner oxide layer on the epitaxial silicon layer; and   an oxide material filing the void within the linear oxide layer and pad nitride film.   
   
   
       12 . A shallow trench isolation of  claim 11 , wherein the voltage characteristic anomaly attenuating means comprises rounded edge on a top portion of the epitaxial silicon layer adjacent to an opening edge of the trench.