Internal address generator

Abstract

An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

1 - 25 . (canceled) 
   
   
       26 . An internal address generator for use in a semiconductor memory device, comprising:
 a first shift register unit configured to output an internal read address based on an input address and an additive latency information signal;   a second shift register unit configured to output an internal write address based on the internal read address and a column address strobe (CAS) latency information signal;   a first controller configured to generate a read drive clock for enabling the first shift register unit based on a clock and a first additive latency information signal; and   a second controller configured to generate a write drive clock for enabling the second shift register unit based on an inverted clock and a write enable signal.   
   
   
       27 . The internal address generator as recited in  claim 26 , wherein the write enable signal is activated during a write operation. 
   
   
       28 . The internal address generator as recited in  claim 27 , wherein the first additive latency information signal is activated when the additive latency is zero clocks. 
   
   
       29 . The internal address generator as recited in  claim 28 , wherein the first controller includes:
 a first inverter for inverting the clock;   a second inverter for inverting the first additive latency information signal;   a first logic gate for logically combining outputs of the first and the second inverters; and   a first inverter chain for delaying an output of the first logic gate to thereby output the read drive clock.   
   
   
       30 . The internal address generator as recite in  claim 29 , wherein the second controller includes:
 a third inverter for inverting the clock;   a second logic gate for logically combining an output of the first inverter and the write enable signal; and   a second inverter chain for delaying an output of the second logic gate to output the write drive clock.