Method of forming double gate dielectric layers and semiconductor device having the same

Abstract

A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.

1 - 6 . (canceled) 
   
   
       7 . A semiconductor device comprising:
 a silicon substrate having a field region defining an active region, the silicon substrate having a high voltage area and a low voltage area;   source/drain regions formed in the active region of the substrate, in each of the high and low voltage areas;   double gate dielectric layers formed between the source/drain regions on the substrate, in each of the high and low voltage areas, and including an underlying oxide layer having a first thickness and an overlying oxy-nitride layer having a second thickness smaller than the first thickness; and   a gate electrode formed on the double gate dielectric layers, in each of the high and low voltage areas.   
   
   
       8 . The device of  claim 7 , wherein a thickness of the double dielectric layer in the high voltage area is different from a thickness of the double dielectric layer in the low voltage area. 
   
   
       9 . The device of  claim 7 , wherein a thickness of the double dielectric layer in the high voltage area is greater than a thickness of the double dielectric layer in the low voltage area. 
   
   
       10 . The device of  claim 8 , wherein a thickness of the oxide layer in the high voltage area is greater than a thickness of the oxide layer in the low voltage area. 
   
   
       11 . The device of  claim 7 , further comprising dielectric spacers formed on sidewalls of the gate electrode.