SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2

Abstract

To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO 2 ) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO 2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO 2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

1 . A semiconductor device structure comprising:
 a first active region containing a semiconductor material;   a second active region containing the semiconductor material; and   a shallow trench isolation region separating the first and second active regions, the shallow trench isolation region containing liquid-phase deposited silicon dioxide that is free of growth seams.   
     
     
         2 . The semiconductor device structure of  claim 1  further comprising:
 a buried oxide layer supporting the first and second active regions.   
     
     
         3 . The semiconductor device structure of  claim 2  wherein the shallow trench isolation region includes sidewalls extending to the buried oxide layer to define the first and second active regions. 
     
     
         4 . The semiconductor device structure of  claim 3  wherein the sidewalls are substantially free of native oxide. 
     
     
         5 . The semiconductor device structure of  claim 1  further comprising:
 a pad oxide layer on the first and second active regions.   
     
     
         6 . The semiconductor device structure of  claim 5  wherein the pad oxide layer has a thickness between approximately 2 nm and approximately 10 nm. 
     
     
         7 . The semiconductor device structure of  claim 1  further comprising:
 a pad nitride layer on the first and second active regions.   
     
     
         8 . The semiconductor device structure of  claim 7  wherein the pad nitride layer has a thickness between approximately 10 nm and approximately 150 nm. 
     
     
         9 . The semiconductor device structure of  claim 1  wherein the liquid-phase deposited silicon dioxide has a density similar to thermally grown silicon dioxide. 
     
     
         10 . A semiconductor device structure comprising:
 a first active region;   a second active region; and   a shallow trench isolation region separating the first and second active regions, the shallow trench isolation region filled by an electrically-insulative material containing silicon dioxide configured to have a uniform etch rate when exposed to wet etching solution.   
     
     
         11 . The semiconductor device structure of  claim 10  further comprising:
 a buried oxide layer supporting the first and second active regions.   
     
     
         12 . The semiconductor device structure of  claim 11  wherein the shallow trench isolation region includes sidewalls extending to the buried oxide layer to define the first and second active regions. 
     
     
         13 . The semiconductor device structure of  claim 12  wherein the sidewalls are substantially free of native oxide. 
     
     
         14 . The semiconductor device structure of  claim 10  further comprising:
 a pad oxide layer on the first and second active regions.   
     
     
         15 . The semiconductor device structure of  claim 14  wherein the pad oxide layer has a thickness between approximately 2 nm and approximately 10 nm. 
     
     
         16 . The semiconductor device structure of  claim 10  further comprising:
 a pad nitride layer on the first and second active regions.   
     
     
         17 . The semiconductor device structure of  claim 16  wherein the pad nitride layer has a thickness between approximately 10 nm and approximately 150 nm. 
     
     
         18 . The semiconductor device structure of  claim 10  wherein the liquid-phase deposited silicon dioxide has a density similar to thermally grown silicon dioxide. 
     
     
         19 . The semiconductor device structure of  claim 10  wherein the electrically-insulative material is liquid-phase deposited silicon dioxide.