Method of operating non-volatile memory

Abstract

A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

What is claimed is: 
     
         1 . A method of operating a non-volatile memory array having a plurality of memory cell arrays, each memory cell array comprising: a plurality of select gate structures disposed on a substrate, each select gate structure comprising a select gate dielectric layer and a select gate formed on the substrate and a trench in the substrate between two adjacent select gates; a composite layer covering the substrate and the select gates and comprising a charge-trapping layer; a plurality of control gates disposed on the composite layer and filling the trench between adjacent select gates; a plurality of word lines arranged in a row direction and coupled to the control gates in the same row; a plurality of select gate lines arranged in parallel in the column direction and coupled to the select gates on the same column; a plurality of bit lines arranged in parallel in the column direction such that the bit lines are formed in the substrate underneath the select gate lines when a voltage is applied to the select gate lines; a pair of adjacent select gates, wherein the control gate between two adjacent select gates and the composite layer together form a plurality of memory cells and each pair of neighboring memory cells share a common select gate line; and the composite layer between the control gate of each memory cell and a first sidewall of a corresponding trench constituting a first bit storage and the composite layer between the control gate of each memory cell and a second sidewall of a corresponding trench constituting a second bit storage, the method comprising:
 performing a programming operation by applying a first voltage to a selected word line coupled to a selected memory cell; applying a second voltage to a first selected select gate line adjacent to the selected memory cell on the first bit side; applying a third voltage to a second selected select gate line next to the first selected select gate line on the first bit side so that a first selected bit line is formed in the substrate underneath the second selected select gate line; applying a fourth voltage to the first selected bit line; applying a fifth voltage to a third selected select gate line adjacent to the selected memory cell on the second bit side so that a second selected bit line is formed in the substrate underneath the third selected select gate line; applying a sixth voltage to the second selected bit line; applying a seventh voltage to a fourth selected select gate line next to the third selected select gate line on the second bit side, and applying a 0V to the unselected select gate lines, wherein the second voltage is close to the threshold voltage of the select gate line, the fifth voltage and the third voltage is higher than the second voltage, the sixth voltage is higher than the fourth voltage, and the first voltage is higher than the second voltage so that the first bit is programmed through source side injection.   
     
     
         2 . The method of  claim 1 , wherein the first voltage is about 10V, the second voltage is about 1V, the third voltage is about 5V, the fourth voltage is about 0V, the fifth voltage is about 8V, the sixth voltage is about 4.5V, and the seventh voltage is about 0V. 
     
     
         3 . The method of  claim 1 , farther comprising:
 performing a programming operation by applying a eighth voltage to the selected word line coupled to the selected memory cell; applying a ninth voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side; applying a tenth voltage to the fourth selected select gate line next to the third selected select gate line on the second bit side so that a third selected bit line is formed in the substrate underneath the fourth selected select gate line; applying a eleventh voltage to the third selected bit line; applying a twelfth voltage to the first selected select gate line adjacent to the selected memory cell on the first bit side so that a fourth selected bit line is formed in the substrate underneath the first selected select gate line; applying a thirteenth voltage to the fourth selected bit line; applying a fourteenth voltage to the second selected select gate line next to the first selected select gate line on the first bit side, and applying 0V to the unselected select gate lines, wherein the ninth voltage is close to the threshold voltage of the select gate line, the twelfth voltage and the tenth voltage is higher than the ninth voltage, the thirteenth voltage is higher than the eleventh voltage, and the eighth voltage is higher than the ninth voltage, so that the second bit is programmed through source side injection.   
     
     
         4 . The method of  claim 3 , wherein the eighth voltage is about 10V, the ninth voltage is about 1V, the tenth voltage is about 5V, the eleventh voltage is about 0V, the twelfth voltage is about 8V, the thirteenth voltage is about 4.5V, and the fourteenth voltage is about 0V. 
     
     
         5 . The method of  claim 1 , further comprising:
 performing an erasing operation by applying an eighth voltage to the word lines and applying a ninth voltage to the substrate, and making the select gate lines floating so that the electrons stored within the composite layers are tunnelled into the substrate, wherein the voltage differential between the eighth voltage and the ninth voltage triggers FN tunneling effect.   
     
     
         6 . The method of  claim 5 , wherein the voltage differential is between about −12V to −20V. 
     
     
         7 . The method of  claim 6 , wherein the eighth voltage is about −15V and the ninth voltage is about 0V. 
     
     
         8 . The method of  claim 1 , further comprising:
 performing a reading operation by applying a eighth voltage to the selected word line coupled to the selected memory cell; applying an ninth voltage to the first selected select gate line adjacent to the selected memory cell on first bit side so that a third selected bit line is formed in the substrate underneath the first selected select gate line; applying a tenth voltage to a third selected bit line; applying a eleventh voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; applying a twelfth voltage to the second selected bit line and reading out the first bit, wherein the ninth voltage and the eleventh voltage is higher than the twelfth voltage, the twelfth voltage is higher than the tenth voltage, and the eighth voltage is higher than the threshold voltage of the memory cells without trapping electrons but smaller than the threshold voltage of the memory cells containing trapped electrons.   
     
     
         9 . The method of  claim 8 , wherein the eighth voltage is about 3V, the ninth voltage and the eleventh voltage are about 5V, the tenth voltage is about 0V and the twelfth voltage is about 1.5V. 
     
     
         10 . The method of  claim 8 , further comprising:
 performing a reading operation by applying a thirteenth voltage to a selected word line coupled to the selected memory cell; applying a fourteenth voltage to the third selected select gate line adjacent to the selected memory cell on the second bit side so that the second selected bit line is formed in the substrate underneath the third selected select gate line; applying a fifteenth voltage to the second selected bit line; applying a sixteenth voltage to the first selected select gate line adjacent to the selected memory cell on the first bit side so that the third selected bit line is formed in the substrate underneath the first selected select gate line; applying a seventeenth voltage to the third selected bit line and reading out the second bit, wherein the fourteenth voltage and the sixteenth voltage are higher than the seventeenth voltage, the seventeenth voltage is higher than the fifteenth voltage, and the thirteenth voltage is higher than the threshold voltage of the memory cells without trapping electrons but smaller than the threshold voltage of the memory cells containing trapped electrons.   
     
     
         11 . The method of  claim 10 , wherein the thirteenth voltage is about 3V, the fourteenth voltage and the sixteenth voltage are about 5V, the fifteenth voltage is about 0V, and the seventeenth voltage is about 1.5V.