Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same

Abstract

A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown on the lower electrode.

1 . A phase change memory device comprising:
 a storage node including a phase change layer; and   a switching device connected to the storage node; wherein
 the phase change layer is selectively grown on a lower electrode. 
   
   
   
       2 . The phase change memory device of  claim 1 , wherein a seed layer is formed between the lower electrode and the phase change layer, and the phase change layer is formed on the seed layer. 
   
   
       3 . The phase change memory device of  claim 2 , wherein the lower electrode includes,
 a lower electrode contact layer filling a contact hole, and   a connection portion connecting the lower electrode contact layer and the switching device, and wherein
 the lower electrode contact layer is formed between the connection portion and the seed layer. 
   
   
   
       4 . The phase change memory device of  claim 2 , wherein the seed layer is a layer selected from the group consisting of a chalcogenide layer, an electrically conductive transition metal layer, a transition metal nitride layer, a ternary nitride layer and a metal oxide layer. 
   
   
       5 . The phase change memory device of  claim 1 , wherein the phase change layer is formed directly on the lower electrode. 
   
   
       6 . The phase change memory of  claim 5 , wherein the lower electrode includes,
 a lower electrode contact layer filling a contact hole, and   a connection portion connecting the lower electrode contact layer and the switching device, and wherein
 the phase change layer is formed directly on the lower electrode contact layer. 
   
   
   
       7 . The phase change memory device of  claim 5 , the lower electrode and the phase change layer are sequentially stacked to fill a contact hole. 
   
   
       8 . The phase change memory of  claim 7 , wherein the lower electrode includes,
 a lower electrode contact layer, and   a connection portion connecting the lower electrode contact layer and the switching device, and wherein
 the lower electrode contact layer and the phase change layer are sequentially stacked to fill the contact hole. 
   
   
   
       9 . The phase change memory device of  claim 8 , wherein the lower electrode contact layer is formed in a first portion of the contact hole and the phase change layer is formed in a second portion of the contact hole. 
   
   
       10 . The phase change memory device of  claim 9 , wherein the first portion of the contact hole includes the entire lower electrode contact layer and the second portion of the contact hole includes the phase change layer. 
   
   
       11 . A method of manufacturing a phase change memory device, the method comprising:
 forming an insulating interlayer on a semiconductor substrate including a switching device, the insulating interlayer being formed to cover the switching device;   forming a lower electrode connected to the switching device; and   selectively growing a phase change layer on the lower electrode.   
   
   
       12 . The method of  claim 11 , wherein the phase change layer is a layer selected from the group consisting of a Ge—Sb—Te layer, a As—Sb—Te layer, a As—Ge—Sb—Te layer, a Sn—Sb—Te layer, a (the group 5A element)-Sb—Te layer, a (the group 6A element)-Sb—Te layer, a (the group 5A element)-Sb—Se layer, and a (the group 6A element)-Sb—Se layer. 
   
   
       13 . The method of  claim 11 , wherein before the forming of the insulating interlayer, the method further includes,
 forming a transistor as the switching device on the substrate,   forming a lower insulating interlayer covering the transistor,   forming a contact pad layer in the lower insulating interlayer, the contact pad layer being connected to a source or a drain of the transistor, and   forming a conductive plug electrically connecting the contact pad layer and the lower electrode.   
   
   
       14 . The method of  claim 11 , wherein the growing the phase change layer further includes,
 forming a seed layer on the lower electrode, and wherein   the phase change layer is selectively grown on the seed layer.   
   
   
       15 . The method of  claim 14 , wherein the seed layer is a layer selected from the group consisting of a chalcogenide layer, an electrically conductive transition metal layer, a transition metal nitride layer, a ternary nitride layer, and a transition metal oxide layer. 
   
   
       16 . The method of  claim 14 , further including,
 forming an insulation layer surrounding side walls of the phase change layer and the seed layer after selectively growing the phase change layer.   
   
   
       17 . The method of  claim 16 , wherein the forming of the insulation layer includes,
 forming an insulation layer covering the phase change layer and the seed layer, and   planarizing a top surface of the insulation layer to expose the phase change layer.   
   
   
       18 . The method of  claim 11 , wherein forming the lower electrode further includes,
 forming a connection portion on the switching device, and   forming a lower electrode contact layer on the connection portion, wherein   the phase change layer is selectively grown directly on the lower electrode contact layer.   
   
   
       19 . The method of  claim 18 , wherein the lower electrode contact layer is formed of a layer selected from the group consisting of a chalcogenide layer, an electrically conductive transition metal layer, a transition metal nitride layer, a silicide layer, a ternary nitride layer, and a transition metal oxide layer. 
   
   
       20 . The method of  claim 19 , wherein the chalcogenide layer is a layer selected from the group consisting of a Ge layer, a Sb layer, a GeTe layer, a GeSbTe layer, a Ge—Sb—Te—N layer, a As—Sb—Te—N layer, a As—Ge—Sb—Te—N layer, a Sn—Sb—Te—N layer, a (the group 5A element)-Sb—Te—N layer, a (the group 6A element)-Sb—Te—N layer, a (the group 5A element)-Sb—Se—N layer, and a (the group 6A element)-Sb—Se—N layer. 
   
   
       21 . The method of  claim 18 , further including,
 forming an upper insulating interlayer including a contact hole, and wherein   the lower electrode contact layer and the phase change layer are formed to fill the contact hole.   
   
   
       22 . The method of  claim 21 , wherein the forming of the phase change layer further includes,
 planarizing the phase change layer after sequentially filling the contact hole with the lower electrode contact layer and the phase change layer.   
   
   
       23 . The method of  claim 22 , wherein after the planarizing of the top surface of the insulation layer, the method further includes,
 sequentially forming a barrier layer covering an exposed portion of the phase change layer and an upper electrode on the insulation layer.