Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays

Abstract

A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.

1 . A delay-locked loop for receiving an external clock signal and synchronizing a phase of a feedback clock signal with a phase of the external clock signal, the delay-locked loop comprising:
 a phase detector for comparing the phase of the external clock signal with the phase of the feedback clock signal and outputting a phase difference as an error control signal;   a delay line, comprising a plurality of delay cells having various unit time delays, for receiving the external clock signal, controlling the phase of the external clock signal to obtain an output clock signal and outputting the output clock signal, wherein the number of delay cells in operation is adjusted in response to a predetermined shift signal; and   a filter unit for generating the shift signal for selecting the number of delay cells in operation in the delay line, in response to the error control signal,   wherein each delay cell is a differential amplifier and adjusts a resistance connected to a power supply voltage to vary the unit time delay, and   wherein the differential amplifier comprises one of
 an input transistor, to which the external clock signal is transmitted, having a size that gradually increases from the delay cell of a front end of the delay line to the delay cell of a rear end of the delay line, and 
 a capacitor at an output end, wherein a capacitance of the capacitor gradually increases from the delay cell of a front end of the delay line to the delay cell of a rear end of the delay line. 
   
   
   
       2 . A synchronous mirror delay comprising:
 a forward delay array (FDA), comprising a plurality of delay cells having various unit time delays, for receiving an external clock signal and generating a forward delay clock signal by forward delaying a phase of the external clock signal;   a mirror control circuit for delaying and outputting the forward delay clock signal in response to the forward delay clock signal and the external clock signal; and   a backward delay array (BDA), comprising a plurality of serially connected delay cells having various unit time delays, for receiving an output of the mirror control circuit and generating a backward delay clock signal by backward delaying a phase of an output of the mirror control circuit.   
   
   
       3 . The synchronous mirror delay of  claim 2 , wherein the plurality delay cells of the forward delay array and backward delay array have unit time delays that gradually increased from the delay cell of a front end of the respective array to the delay cell of a rear end of the respective array. 
   
   
       4 . The synchronous mirror delay of  claim 2 , wherein each delay cell comprises a NAND gate and an inverter that are connected in series, and wherein the unit time delay is varied according to the sizes of the transistors of the NAND gate and the inverter. 
   
   
       5 . The synchronous mirror delay of  claim 4 , wherein a size of the transistor is gradually increased from the delay cell at a front end of the array to the delay cell at a rear end of the array, wherein the array is at least one of the forward delay array and the backward delay array. 
   
   
       6 . The synchronous mirror delay of  claim 4 , wherein each delay cell comprises a capacitor at an output end,
 and wherein the capacitance of the capacitor gradually increases from the delay cell at the front end of the array to the delay cell at the rear end of the array, wherein the array is at least one of the forward delay array and the backward delay array.   
   
   
       7 . The synchronous mirror delay of  claim 2 , wherein the forward delay array and the backward delay array comprise even-numbered delay cells have longer unit time delays than odd-numbered delay cells. 
   
   
       8 . The synchronous mirror delay of  claim 2 , wherein the forward delay array and the backward delay array comprise odd-numbered delay cells have longer unit time delays than even-numbered delay cells. 
   
   
       9 . A time delay compensation circuit for synchronizes an output clock signal with an external clock signal, the time delay compensation circuit comprising:
 a delay unit, comprising a plurality of delay cells having various unit time delays, for receiving the external clock signal and generating the output clock signal in synchronization with the external clock signal; and   a control unit for selecting a number of delay cells in the delay unit and controlling the number of delay cells in operation such that the output clock signal is synchronized with the external clock signal,   wherein the delay unit comprises one of even-numbered delay cells having longer unit time delays than odd-numbered delay cells and odd-numbered delay cells have longer unit time delays than even-numbered delay cells.