Electropolishing metal features on a semiconductor wafer

Abstract

In one embodiment, the present invention includes a method for electroplating a plurality of metal bumps on a device side of a semiconductor wafer and planarizing the metal bumps by electropolishing to obtain a substantially uniform thickness for the plurality of metal bumps. Other embodiments are described and claimed.

1 . A method comprising:
 forming a barrier layer over a semiconductor wafer;   forming a conductive stack layer over the barrier layer;   patterning a mask layer over the conductive stack layer to expose a portion of the conductive stack layer;   electroplating a plurality of conductive features over the exposed conductive stack layer; and   electropolishing the plurality of conductive features by applying an anodic current to the semiconductor wafer, wherein at least a portion of the semiconductor wafer is located in an electrolytic solution.   
     
     
         2 . The method of  claim 1 , further comprising removing the patterned mask layer before electropolishing the plurality of conductive features, wherein the electropolishing removes at least a portion of the conductive stack layer and the plurality of conductive features to obtain a substantially uniform height for the plurality of conductive features. 
     
     
         3 . The method of  claim 1 , further comprising applying the anodic current for a predetermined time period. 
     
     
         4 . The method of  claim 1 , further comprising applying the anodic current at a first level for a first predetermined time period and at a second level for a second predetermined time period. 
     
     
         5 . The method of  claim 4 , further comprising applying the anodic current through an anode electrode coupled to an edge portion of the barrier layer. 
     
     
         6 . The method of  claim 5 , wherein the barrier layer comprises a non-copper conductive material, the conductive stack layer comprises copper, and the plurality of conductive features comprises copper, and further comprising removing the conductive stack layer while electropolishing the plurality of conductive features, wherein the plurality of conductive features is etched at a first rate when the conductive stack layer is present and at a second rate when the conductive stack layer is not present. 
     
     
         7 . A method comprising:
 electroplating a plurality of metal bumps on a device side of a semiconductor wafer, the plurality of metal bumps comprising interconnects to a package or a second die; and   planarizing the plurality of metal bumps by electropolishing to obtain a substantially uniform thickness for the plurality of metal bumps.   
     
     
         8 . The method of  claim 7 , further comprising:
 forming a barrier layer on the device side of the semiconductor wafer;   forming a conductive stack layer over the barrier layer; and   patterning a mask layer over the conductive stack layer to expose a portion of the conductive stack layer and electroplating the metal bumps on the exposed portion of the conductive stack layer.   
     
     
         9 . The method of  claim 8 , wherein the barrier layer comprises a non-copper conductive material, the conductive stack layer comprises copper, and the plurality of metal bumps comprises copper, and further comprising removing the conductive stack layer while electropolishing the plurality of metal bumps, wherein the plurality of metal bumps is etched at a first rate when the conductive stack layer is present and at a second rate when the conductive stack layer is not present. 
     
     
         10 . The method of  claim 8 , further comprising planarizing the plurality of metal bumps while the patterned mask layer covers at least a portion of the semiconductor wafer not having the plurality of metal bumps. 
     
     
         11 . The method of  claim 8 , wherein the plurality of metal bumps comprises copper bumps for interconnection to the package. 
     
     
         12 . The method of  claim 8 , wherein the plurality of metal bumps comprises through silicon vias for interconnection to the second die. 
     
     
         13 . The method of  claim 8 , further comprising applying an electrical current to the barrier layer, the barrier layer comprising a non-copper metal, the plurality of metal bumps comprising copper bumps formed over the barrier layer, wherein the semiconductor wafer is at least partially immersed in an electrolytic solution during the electropolishing. 
     
     
         14 . The method of  claim 13 , wherein the electrolytic solution comprises phosphoric acid, polyethylene glycol, and at least one of citric acid and ethylenediaminetetraacetic acid (EDTA).