Manufacturing method of dynamic random access memory

Abstract

A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.

1 . A manufacturing method of a dynamic random access memory, comprising:
 forming a deep trench in a substrate by performing a patterning process and using a patterned mask layer on the substrate as a mask;   forming a bottom electrode in the substrate at a bottom of the deep trench;   forming a capacitor dielectric layer and a first conductive layer in the deep trench sequentially;   forming a first collar oxide layer on a sidewall of the deep trench exposed by the first conductive layer;   filling the deep trench with a second conductive layer, wherein a height of the second conductive layer is substantially equivalent to a height of the first collar oxide layer;   filling the deep trench with a first dielectric layer;   removing a part of the patterned mask layer, a part of the substrate and a part of the first dielectric layer to form a first trench for exposing a part of the second conductive layer;   forming a second collar oxide layer on a sidewall of the first trench;   filling the first trench with a third conductive layer, wherein the height of the third conductive layer is substantially equivalent to the height of the second collar oxide layer;   filling up the first trench with a second dielectric layer;   removing the patterned mask layer;   forming a gate structure over the deep trench;   forming a second trench in the second dielectric layer at one side of the gate structure to expose the third conductive layer; and   forming a fourth conductive layer over the substrate, and filling up the second trench with the fourth conductive layer.   
   
   
       2 . The manufacturing method of a dynamic random access memory as claimed in  claim 1 , wherein the method of forming the fourth conductive layer comprises a selective epitaxial silicon growth process. 
   
   
       3 . The manufacturing method of a dynamic random access memory as claimed in  claim 1 , wherein the method of forming the first dielectric layer comprises:
 forming a dielectric material layer on the substrate;   performing a rapid thermal annealing process; and   performing a chemical-mechanical polishing process.   
   
   
       4 . The manufacturing method of a dynamic random access memory as claimed in  claim 1 , wherein the method of forming the bottom electrode comprises:
 forming a doped oxide layer on the sidewall of the deep trench; and   performing a thermal process.   
   
   
       5 . The manufacturing method of a dynamic random access memory as claimed in  claim 4 , wherein the doped oxide layer comprises dopants of arsenic ions. 
   
   
       6 . The manufacturing method of a dynamic random access memory as claimed in  claim 1 , wherein the method of forming the second dielectric layer comprises a high density plasma chemical vapor deposition (HDPCVD) process. 
   
   
       7 . A manufacturing method of a dynamic random access memory, comprising:
 forming a first trench in a substrate;   forming a first conductive layer in the first trench;   forming a second trench in the substrate, wherein a depth of the second trench is smaller than a depth of the first trench, and the second trench partially overlaps with the first trench;   forming a second conductive layer in the second trench;   forming a third trench in the substrate and above the second trench, wherein the third trench is shallower than the second trench; and   forming a third conductive layer in the third trench and on the surface of the substrate, wherein the second conductive layer is electrically connected with one side of a gate structure through the third conductive layer.   
   
   
       8 . The manufacturing method of a dynamic random access memory as claimed in  claim 7 , further comprising forming a collar oxide layer on a sidewall of the second trench. 
   
   
       9 . The manufacturing method of a dynamic random access memory as claimed in  claim 7 , wherein the method of forming the second trench comprises:
 forming a first dielectric layer in the first trench; and   removing a part of the substrate and a part of the first dielectric layer to form an opening exposing a part of the first conductive layer.   
   
   
       10 . The manufacturing method of a dynamic random access memory as claimed in  claim 7 , wherein the method of forming the third trench comprises:
 forming a second dielectric layer in the second trench; and   removing a part of the second dielectric layer to form an opening exposing a part of the second conductive layer.   
   
   
       11 . The manufacturing method of a dynamic random access memory as claimed in  claim 7 , wherein the method of forming the third conductive layer comprises performing a selective epitaxial silicon growth process. 
   
   
       12 . The manufacturing method of a dynamic random access memory as claimed in  claim 7 , wherein a photomask used for forming the third trench is the same as a photomask used for forming the second trench.