Semiconductor package

Abstract

There is disclosed a method of making an electronic package ( 10 ) by: forming a metal base ( 50 ) on which to build the components of an electronic package; applying a mask layer ( 60 ) on the base to an area that is not to be occupied by interconnection pads ( 200 ) or die attachment pads ( 201 ) of the package; plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads ( 200, 201 ); removing the mask layer; mounting a semiconductor die ( 302 ) to at least one die attachment pad ( 201 ); electrically connecting the semiconductor die ( 302 ) to one or more interconnection pads ( 200 ); embedding the components on the base in an encapsulation material ( 300 ) to form a package; removing the metal base ( 50 ) to leave a package panel; and cutting the panel into discrete package units.

1 . A method of making an electronic package ( 10 ) characterised by:
 forming a metal base ( 50 ) on which to build the components of an electronic package;   applying a mask layer ( 60 ) on the base to an area that is not to be occupied by interconnection pads ( 200 ) or die attachment pads ( 201 ) of the package;   plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads ( 200 ,  201 );   removing the mask layer;   mounting a semiconductor die ( 302 ) to at least one die attachment pad ( 201 );   electrically connecting the semiconductor die ( 302 ) to one or more interconnection pads ( 200 );   embedding the components on the base in an encapsulation material ( 300 ) to form a package;   removing the metal base ( 50 ) to leave a package panel; and   cutting the panel into discrete package units.   
     
     
         2 . The method of  claim 1  characterised by applying a mask layer ( 60 ) that is photo resistant and/or heat resistant. 
     
     
         3 . The method of  claim 1  or  claim 2  characterised by forming the interconnection and die attachment pads by first plating a solderable layer ( 51 ) on the base ( 50 ), followed by plating a pad layer ( 53 ) on the solderable layer and plating an interconnection layer ( 54 ) on the pad layer. 
     
     
         4 . The method of  claim 3  characterised by plating a barrier layer ( 52 ) between the solderable layer ( 51 ) and pad layer ( 53 ) and/or between the pad layer ( 53 ) and interconnection layer ( 54 ). 
     
     
         5 . The method claimed in  claim 3  or  claim 4  characterised by combining two or more metals to form a layer. 
     
     
         6 . The method claimed in any one of  claims 3  to  5  characterised by using copper as the material for the base. 
     
     
         7 . The method claimed in any one of  claims 3  to  6  characterised by using gold or gold strike as the material for the solderable layer. 
     
     
         8 . The method claimed in any one of  claims 3  to  7  characterised by using nickel or copper for the material for the pad layer. 
     
     
         9 . The method claimed in any one of  claim 3  to  8  characterised by using gold or silver as the material for the interconnection layer. 
     
     
         10 . The method claimed in any one of  claims 3  to  9  characterised by using palladium or nickel palladium as the material for the barrier layer. 
     
     
         11 . The method claimed in any one of the preceding claims characterised by electrically connecting the semiconductor die to one or more interconnection pads using wirebonds ( 202 ). 
     
     
         12 . The method claimed in any one of  claims 1  to  10  characterised by electrically connecting the semi conductor die to one or more interconnection pads using flip chip bumps ( 203 ) pre-attached to the semiconductor die. 
     
     
         13 . The method claimed in  claim 12  characterised by after removing the mask layer depositing flux or solder ( 81 ) on at least one interconnection pad ( 200 ) and at least one die attachment pad ( 201 ); and
 mounting a flip chip semiconductor die ( 302 ) onto the flux or solder to form an electrical connection between the semiconductor die and at least one interconnection pad.   
     
     
         14 . The method claimed in any one of the preceding claims characterised by forming interconnection and die attachment pads protruding from the underside of the package by carrying out the following steps inbetween the steps of forming a metal base and applying a mask layer ( 60 ):
 applying an additional mask layer ( 61 ) on the base ( 50 ) to the areas that are to be occupied by the interconnection and die attachment pads of the package;   plating the remaining exposed areas of the base with the metal base material ( 50 ) to increase the thickness of the base inbetween where the interconnection and die attachment pads are to be formed; and   removing the additional mask layer ( 61 ).   
     
     
         15 . The method claimed in any one of the preceding claims characterised by applying a solder finish ( 204 ) to the exposed interconnection and die attachment pads on the underside of the package after removal of the base. 
     
     
         16 . The method claimed in  claim 15  characterised by mounting the package panel in a dipping jig and dipping the underside of the package into molten solder before cutting the panel into discrete package units. 
     
     
         17 . The method claimed in any one of the preceding claims characterised by forming the interconnection pads and die attachment pads with an enlarged “mushroom” head. 
     
     
         18 . The method claimed in  claim 17  characterised by forming the enlarged head by plating the layers of metal forming the interconnection and die attachment pads over and above the top of the mask layer such that the head flares over the mask layer. 
     
     
         19 . An semiconductor package ( 10 ) made according to the method of  claim 1  characterised in that the package comprises a semi conductor die ( 302 ) mounted on a die attachment pad ( 201 ) and electrically connected to at least one interconnection pad ( 200 ) by an electrical connection, all embedded in an encapsulation material ( 300 ). 
     
     
         20 . The semiconductor package claimed in  claim 19  characterised in that the mask layer ( 60 ) used in making the package is photo resistant and/or heat resistant. 
     
     
         21 . The semiconductor package claimed in  claims 19  or  20  characterised in that the layers of metal forming the interconnection and die attachment pads include a solderable layer ( 51 ), a pad layer ( 53 ) and an interconnection layer ( 54 ). 
     
     
         22 . The semiconductor package claimed in  claim 21  characterised in that a barrier layer ( 52 ) is plated inbetween any two of the solderable layer, interconnection layer and pad layer. 
     
     
         23 . The semiconductor package claimed in either  claim 21  or  claim 22  characterised in that the base is made of copper. 
     
     
         24 . The semiconductor package claimed in any one of  claims 21  to  23  characterised in that the solderable layer is made of gold or gold strike. 
     
     
         25 . The semiconductor package claimed in any one of  claims 21  to  24  characterised in that the pad layer is made of nickel or copper. 
     
     
         26 . The semiconductor package claimed in any one of  claims 21  to  25  characterised in that the interconnection layer is made of gold or silver. 
     
     
         27 . The semiconductor package claimed in any one of  claims 21  to  26  characterised in that the barrier layer is made of palladium or nickel palladium. 
     
     
         28 . The semiconductor package claimed in any one of  claims 21  to  27  characterised in that the base is made of copper. 
     
     
         29 . The semiconductor package claimed in any one of  claims 21  to  28  characterised in that the electrical connection is a wirebond ( 202 ) or a flip chip bump ( 203 ). 
     
     
         30 . The semiconductor package claimed in any one of  claims 21  to  29  characterised in that the interconnection pads and die attachment pads protrude from the underside of the package. 
     
     
         31 . The semiconductor package claimed in any one of  claims 21  to  30  characterised in that a solder finish ( 204 ) is applied to the exposed interconnection pads and die attachment pads on the underside of the package. 
     
     
         32 . The semiconductor package claimed in any one of  claims 21  to  31  characterised in that the interconnection pads and die attachment pads are shaped with an enlarged head to increase the hold on the pads in the encapsulated package.