Rapid Thermal Anneal Equipment and Method Using Sichrome Film

Abstract

A method of determining the degree of calibration of an RTP chamber ( 1 ) includes providing a test wafer having a deposited sichrome layer ( 22 ) of sheet resistance Rsi on an oxide layer ( 21 ) formed on a silicon substrate ( 20 ). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer ( 8 ). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change Rs=Rsi−Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error. The basic technique can be utilized to determine an anneal time and anneal duration for annealing sichrome resistors to precisely adjust the sheet resistance or TCR thereof.

1 . A method of adjusting a resistive parameter of a sichrome resistor in an integrated circuit, comprising:
 (a) providing a sichrome layer on an insulating layer, wherein the insulated layer is formed on a wafer, and wherein_the sichrome layer having a pre-anneal value of the resistive parameter;   (b) placing the wafer in a thermal chamber;   (c) selecting an anneal temperature and an anneal duration corresponding a desired change in value of the sheet resistance parameter from predetermined characterizing information representative of changes in value of the sheet resistance parameter of the sichrome layer as a function of anneal temperature and anneal duration; and   (d) annealing the wafer at the selected anneal temperature for the selected anneal duration so as to cause the desired change in value of the resistive parameter of the sichrome layer so as to provide a desired post-anneal value of the resistive parameter of the sichrome layer.   
   
   
       2 . A method of adjusting the sheet resistance of a sichrome resistor in an integrated circuit, comprising:
 (a) providing a sichrome layer on an insulating layer, wherein the insulated layer is formed on a wafer, and wherein the sichrome layer having a pre-anneal sheet resistance Rsi;   (b) placing the wafer in a thermal chamber;   (c) selecting an anneal temperature and an anneal duration corresponding a desired sheet resistance change ΔRs from predetermined characterizing information representative of ΔRs of the sichrome layer as a function of anneal temperature and anneal duration; and   (d) annealing the wafer at the selected anneal temperature for the selected anneal duration so as to cause the desired sheet resistance change ΔRs of the sichrome layer so as to provide a desired post-anneal sheet resistance Rsf of the sichrome layer.   
   
   
       3 . The method of  claim 2  including obtaining the predetermined characterizing information representative of ΔRs of the sichrome layer by
 i. preparing a batch of sichrome test wafers each having a sichrome layer on an oxide layer formed on a substrate, the sichrome layers having a pre-anneal sheet resistance Rsi;   ii. annealing the test wafers at a various desired anneal temperatures for the predetermined anneal duration;   iii. computing a sheet resistance change ΔRs=Rsi−Rsf of each annealed test wafer caused by the annealing; and   iv. forming groups of ΔRs values of test wafers having the same anneal durations, respectively, to represent ΔRs as a function of anneal temperature for each anneal duration value.   
   
   
       4 . The method of  claim 2  including obtaining the predetermined characterizing information representative of ΔRs of the sichrome layer by
 i. preparing a batch of sichrome test wafers each having a sichrome layer on an oxide layer formed on a substrate, the sichrome layers having a pre-anneal sheet resistance Rsi;   ii. annealing the test wafers at a various desired anneal temperatures for various desired anneal durations, respectively;   iii. computing a sheet resistance change ΔRs=Rsi−Rsf of each annealed test wafer caused by the annealing; and   iv. forming groups of ΔRs values of test wafers having the same anneal durations, respectively, to represent ΔRs as a function of anneal temperature for each anneal duration value.