Semiconductor devices and methods of fabricating the same

Abstract

Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.

1 . A semiconductor device comprising:
 a pad including an electric connection region; and   a protective insulating layer which is formed on the pad and has an aperture exposing the electric connection region;   wherein at least part of a side surface of the protective insulating layer surrounding the electric connection region is a tapered surface with an acute angle to a top surface of the pad;   wherein the protective insulating layer includes at least a first insulating layer and a second insulating layer, each of which has a side surface exposed to the aperture;   wherein the first insulating layer is positioned between the pad and the second insulating layer;   wherein the side surface of the first insulating layer is tapered with an acute angle to the top surface of the pad, and the side surface of the second insulating layer is tapered with an acute angle to the top surface of the pad, and wherein the acute angle of the side surface of the first insulating layer to the top surface is greater than the acute angle of the side surface of the second insulating layer to the top surface; and   wherein the first insulating layer comprises a material having a different etching rate than a material comprising the second insulating layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the angle between the side surface of a portion of the second insulating layer exposed to the aperture and the top surface of the pad is in the range of 30° to 40°. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the first insulating layer comprises a silicon oxide layer and the second insulating layer comprises a silicon nitride layer. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the second insulating layer is larger in thickness than the first insulating layer. 
   
   
       5 . The semiconductor device of  claim 4 , wherein the first insulating layer has a thickness of 400 nm to 600 nm, and the second insulating layer has a thickness of 600 nm to 1400 nm. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the angle between the side surface of a portion of the second insulating layer exposed to the aperture and the top surface of the pad is in the range of 30° to 60°. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the aperture in the second insulating layer has a larger width than the aperture in the first insulating layer. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the first insulating layer includes an exposed upper surface portion, wherein the exposed upper surface portion extends a distance of no greater than 3 nm between an upper end of the side surface of the first insulating layer and a lower end of the side surface of the second insulating layer. 
   
   
       9 . The semiconductor device of  claim 1 , wherein the first insulating layer includes an exposed upper surface portion, wherein the exposed upper surface portion extends a distance of no greater than 1 nm between an upper end of the side surface of the first insulating layer and a lower end of the side surface of the second insulating layer. 
   
   
       10 . A semiconductor device comprising:
 a pad including an electric connection region;   a protective insulating layer on the pad, the protective insulating layer including an aperture exposing the electric connection region;   the protective insulating layer including at least a first insulating layer and a second insulating layer, the first insulating layer being positioned between the pad and the second insulating layer;   the first insulating layer having a first tapered side surface exposed to the aperture, the second insulating layer having a second tapered side surface exposed to the aperture, the first tapered side surface having a different angle with respect to a surface of the pad than the second tapered side surface; and   wherein the first insulating layer comprises a material has a different etching rate than a material comprising the second insulating layer.   
   
   
       11 . The semiconductor device of  claim 10 , wherein the aperture in the second insulating layer has a larger width than the aperture in the first insulating layer. 
   
   
       12 . The semiconductor device of  claim 10 , wherein the first insulating layer comprises a silicon oxide layer and the second insulating layer comprises a silicon nitride layer. 
   
   
       13 . The semiconductor device of  claim 12 , wherein the first insulating layer includes an exposed upper surface portion, wherein the exposed upper surface portion extends a distance of no greater than 3 nm between an upper end of the first tapered side surface and a lower end of the second tapered side surface. 
   
   
       14 . The semiconductor device of  claim 10 , wherein the angle between the second tapered side surface and the surface of the pad is in the range of 30° to 60°, and wherein an angle between the first tapered side surface and the surface of the pad is in the range of 60° to 90°. 
   
   
       15 . The semiconductor device of  claim 10 , wherein the angle between the second tapered side surface and the surface of the pad is in the range of 30° to 40°. 
   
   
       16 . A semiconductor device comprising:
 a pad including an electric connection region;   a protective insulating layer on the pad, the protective insulating layer comprising a first insulating layer and a second insulating layer, the first insulating layer being positioned between the pad and the second insulating layer;   an aperture extending through the first insulating layer and the second insulating layer;   the first insulating layer including a tapered side surface exposed to the aperture;   the second insulating layer including a tapered side surface exposed to the aperture;   the tapered side surface of the first insulating layer having a different angle with respect to a surface of the pad than the tapered side surface of the second insulating layer; and   wherein the first insulating layer comprises a material having a different etching rate than a material comprising the second insulating layer.   
   
   
       17 . The semiconductor device of  claim 16 , wherein the first insulating layer includes an exposed upper surface portion, wherein the exposed upper surface portion extends a distance of no greater than 3 nm between an upper end of the tapered side surface of the first insulating layer and a lower end of the tapered side surface of the second insulating layer. 
   
   
       18 . The semiconductor device of  claim 16 , wherein the first insulating layer comprises a silicon oxide layer and the second insulating layer comprises a silicon nitride layer. 
   
   
       19 . The semiconductor device of  claim 16 , wherein the tapered side surface of the first insulating layer includes an angle with respect to a top surface of the pad in the range of 30° to 60°, and the tapered side surface of the second insulating layer includes an angle with respect to the top surface of the pad in the range of 60° to 90°. 
   
   
       20 . The semiconductor device of  claim 16 , further comprising a barrier layer on the pad in the aperture and a bump bond on the barrier layer.