Shallow trench isolation by atomic-level silicon reconstruction

Abstract

Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms at the surface. The suggested STI region can be used in imager pixel cells or memory device applications.

1 - 30 . (canceled) 
   
   
       31 . A method of forming an isolation region for a semiconductor device, comprising the acts of:
 forming a trench having sidewalls and a bottom in a substrate;   reconstructing a plurality of dangling atomic bonds at said sidewalls to smooth a surface of said sidewalls; and   filling said trench with a dielectric material.   
   
   
       32 . The method of  claim 31 , wherein the reducing act comprises annealing a region including the trench in a noble gas environment. 
   
   
       33 . The method of  claim 31 , wherein the reducing act comprises annealing a region including the trench in a hydrogen gas environment. 
   
   
       34 . The method of  claim 31 , wherein the reducing act comprises performing anisotropic dry etching to form substantially vertical sidewalls for said trench. 
   
   
       35 . The method of  claim 34 , wherein the act of filling said trench with a dielectric material comprises performing a flowable oxide process to fill said trench having vertical sidewalls with an oxide material. 
   
   
       36 . The method of  claim 31 , wherein the reducing act comprises applying a high temperature electric field emission to at least one of said surfaces of said trench to thereby pull silicon atoms from said substrate to said at least one of said surfaces. 
   
   
       37 . The method of  claim 31 , wherein the reducing act comprises sputtering a region at least partially in said trench with an argon gas. 
   
   
       38 . The method of  claim 37 , further comprising the act of annealing said region at a temperature greater than about 1000° C. 
   
   
       39 . The method of  claim 37 , wherein the argon sputtering is performed with an argon beam having a current within the range of about 300 to about 800 eV. 
   
   
       40 . The method of  claim 37 , wherein a rate of said sputtering is within the range of about 10 to about 310 Å/min. 
   
   
       41 . A method of forming a pixel cell comprising:
 forming at least one active area in a substrate; and   forming an isolation region in said substrate adjacent said at least one active area by the acts of:
 forming a trench having surfaces forming sidewalls and a bottom in said silicon substrate; 
 smoothing said surfaces of said sidewalls and said bottom by reducing a plurality of dangling atomic bonds at said surfaces; 
 oxidizing said trench having said smoothed sidewall and bottom surfaces; and 
 filling said trench with a dielectric material. 
   
   
   
       42 . The method of  claim 41 , wherein the reducing act comprises annealing a region including the trench in a noble gas environment. 
   
   
       43 . The method of  claim 41 , wherein the reducing act comprises annealing a region including the trench in a hydrogen gas environment. 
   
   
       44 . The method of  claim 41 , wherein the reducing act comprises performing anisotropic dry etching to form substantially vertical sidewalls for said trench. 
   
   
       45 . The method of  claim 44 , wherein the act of filling said trench with a dielectric material comprises performing a flowable oxide process to fill said trench having vertical sidewalls with an oxide material. 
   
   
       46 . The method of  claim 41 , wherein the reducing act comprises applying a high temperature electric field emission to at least one of said surfaces of said trench to thereby pull silicon atoms from said substrate to said at least one of said surfaces. 
   
   
       47 . The method of  claim 41 , wherein the reducing act comprises sputtering a region at least partially in said trench with an argon gas. 
   
   
       48 . The method of  claim 47 , further comprising the act of annealing said region at a temperature greater than about 1000° C. 
   
   
       49 . The method of  claim 47 , wherein the argon sputtering is performed with an argon beam having a current within the range of about 300 to about 800 eV. 
   
   
       50 . The method of  claim 47 , wherein a rate of said sputtering is within the range of about 10 to about 310 Å/min. 
   
   
       51 . A method of forming a memory device comprising the acts of:
 forming at least two active areas in a substrate; and   forming an isolation region in said substrate between said two active areas, by the acts of:
 forming a trench having surfaces forming sidewalls and a bottom in said substrate; 
 smoothing said surfaces of said sidewalls and said bottom by reducing a plurality of dangling atomic bonds at said surfaces; 
 oxidizing said trench having said smoothed sidewall and bottom surfaces; and 
 filling said trench with a dielectric material. 
   
   
   
       52 . The method of  claim 51 , wherein the reducing act comprises annealing a region including the trench in a noble gas environment. 
   
   
       53 . The method of  claim 51 , wherein the reducing act comprises annealing a region including the trench in a hydrogen gas environment. 
   
   
       54 . The method of  claim 51 , wherein the reducing act comprises performing anisotropic dry etching to form substantially vertical sidewalls for said trench. 
   
   
       55 . The method of  claim 54 , wherein the act of filling said trench with a dielectric material comprises performing a flowable oxide process to fill said trench having vertical sidewalls with an oxide material. 
   
   
       56 . The method of  claim 51 , wherein the reducing act comprises applying a high temperature electric field emission to at least one of said surfaces of said trench to thereby pull silicon atoms from said substrate to said at least one of said surfaces. 
   
   
       57 . The method of  claim 51 , wherein the reducing act comprises sputtering a region at least partially in said trench with an argon gas. 
   
   
       58 . The method of  claim 57 , further comprising the act of annealing said region at a temperature greater than about 1000° C. 
   
   
       59 . The method of  claim 57 , wherein the argon sputtering is performed with an argon beam having a current within the range of about 300 to about 800 eV. 
   
   
       60 . The method of  claim 37 , wherein a rate of said sputtering is within the range of about 10 to about 310 Å/min. 
   
   
       61 . The method of  claim 31 , wherein said step of reducing said dangling atomic bonds smoothes the entire surfaces of said sidewalls and said bottom. 
   
   
       62 . The method of  claim 41 , wherein the step of reducing said dangling atomic bonds smoothes the entire surfaces of said sidewalls and said bottom. 
   
   
       63 . The method of  claim 51 , wherein the step of reducing said dangling atomic bonds smoothes the entire surfaces of said sidewalls and said bottom.