Methods of synchronous digital operation and scan based testing of an integrated circuit using negative edge flip-flops for muxscan and edge clock compatible lssd

Abstract

A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input and a clock pin; and a slave latch having an output, a first clock pin and a second clock pin; capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch; launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.

1 . A method of synchronous digital operation and scan based testing of an integrated circuit, comprising:
 providing a flip-flop comprising:
 a master latch having an input and a clock pin; and 
 a slave latch having an output, a first clock pin and a second clock pin, said slave latch connected to said master latch; 
   capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch;   launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and   capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.   
   
   
       2 . The method of  claim 1 , further including:
 loading data stored in said master latch into said slave latch in response to a third clock signal on said second clock pin of said slave latch or a fourth clock signal on said first clock pin of slave latch.   
   
   
       3 . The method of  claim 2 , said flip-flop further including:
 a first AND gate having a first input, an inverted second input and an output, said output of said first AND gate connected to said first clock pin of said master latch, said second clock signal connected to said first input of said first AND gate; and   a second AND gate having a first input, an inverted second input and an output, said output of said second AND gate connected to said second input of said first AND gate and to said first clock pin of said slave latch, said forth clock signal connected to said first input of said second AND gate, said first clock signal is connected to said second input of said second AND gate; and   said third clock signal connected to said second clock pin of said slave latch;   
   
   
       4 . The method of  claim 1 , further including disabling input to and output from said master latch in response to said second clock signal. 
   
   
       5 . The method of  claim 1 , further including selectively blocking said first clock signal with said second clock signal. 
   
   
       6 . The method of  claim 1 , wherein:
 selectively switching said input of said master latch to either a scan-chain input or to an output of another flip-flop or to a logic circuit of an integrated circuit in response to a control signal.   
   
   
       7 . The method of  claim 6 , wherein said selectively switching said input of said master latch flip-flop is performed with a multiplexer having a first input, a second input, a control input and an output, said output of said multiplexer connected to said input of said master latch, said first input of said multiplexer connected to either said scan-chain input or to said output of said another flip-flop and said second input of said multiplexer connected to said logic circuit of said integrated circuit. 
   
   
       8 . The method of  claim 1 , said master latch further including an additional input and an additional clock input. 
   
   
       9 . The method of  claim 8 , wherein:
 said input of said master latch is connected to either a scan-chain input or to an output of another flip-flop;   said additional input of said master latch is connected to a logic circuit of said integrated circuit, said flip-flop and said integrated circuit on a same integrated circuit chip; and   capturing data presented on said additional input of said master latch in response to a fifth clock signal on said additional pin of said master latch.