Inventor · disambiguated record
David E. Lackey
Also filed as: LACKEY DAVID · LACKEY DAVID E
45 granted patents·3 pending applications·1,011 citations·filing 1990–2012
98Inventor score
Top patents by PatentIndex Score
48 records- 0195US6883152B2Voltage island chip implementationIBM·Filed 2004·Granted Apr 19, 2005·92 cites·20 claims
- 0295US6820240B2Voltage island chip implementationIBM·Filed 2002·Granted Nov 16, 2004·90 cites·14 claims
- 0395US6577156B2Method and apparatus for initializing an integrated circuit using compressed data from a remote fuseboxIBM·Filed 2000·Granted Jun 10, 2003·106 cites·28 claims
- 0495US6300809B1Double-edge-triggered flip-flop providing two data transitions per clock cycleIBM·Filed 2000·Granted Oct 9, 2001·68 cites·6 claims
- 0594US6779163B2Voltage island design planningIBM·Filed 2002·Granted Aug 17, 2004·89 cites·31 claims
- 0693US7620921B2IC chip at-functional-speed testing with process coverage evaluationIBM·Filed 2007·Granted Nov 17, 2009·33 cites·30 claims
- 0789US8543966B2Test path selection and test program generation for performance testing integrated circuit chipsBICKFORD JEANNE P·Filed 2011·Granted Sep 24, 2013·8 cites·24 claims
- 0889US6792582B1Concurrent logical and physical construction of voltage islands for mixed supply voltage designsIBM·Filed 2000·Granted Sep 14, 2004·65 cites·61 claims
- 0988US6609228B1Latch clustering for power optimizationIBM·Filed 2000·Granted Aug 19, 2003·59 cites·21 claims
- 1087US6567943B1D flip-flop structure with flush path for high-speed boundary scan applicationsIBM·Filed 2000·Granted May 20, 2003·41 cites·27 claims
- 1186US8423847B2Microcontroller for logic built-in self test (LBIST)GRISE GARY D·Filed 2012·Granted Apr 16, 2013·5 cites·17 claims
- 1283US8589843B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Nov 19, 2013·4 cites·13 claims
- 1382US7996807B2Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and methodIBM·Filed 2008·Granted Aug 9, 2011·11 cites·20 claims
- 1479US8490045B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Jul 16, 2013·3 cites·22 claims
- 1579US5146460ALogic simulation using a hardware accelerator together with an automated error event isolation and trace facilityIBM·Filed 1990·Granted Sep 8, 1992·120 cites·15 claims
- 1678US7856607B2System and method for generating at-speed structural tests to improve process and environmental parameter space coverageIBM·Filed 2007·Granted Dec 21, 2010·8 cites·25 claims
- 1777US7490280B2Microcontroller for logic built-in self test (LBIST)IBM·Filed 2006·Granted Feb 10, 2009·6 cites·10 claims
- 1877US7381986B2Arrangement for testing semiconductor chips while incorporated on a semiconductor waferIBM·Filed 2006·Granted Jun 3, 2008·6 cites·8 claims
- 1976US8490040B2Disposition of integrated circuits using performance sort ring oscillator and performance path testingBICKFORD JEANNE P·Filed 2011·Granted Jul 16, 2013·3 cites·29 claims
- 2076US8122409B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2007·Granted Feb 21, 2012·5 cites·10 claims
- 2176US7487487B1Design structure for monitoring cross chip delay variation on a semiconductor deviceIBM·Filed 2008·Granted Feb 3, 2009·8 cites·1 claims
- 2275US7560964B2Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibilityIBM·Filed 2005·Granted Jul 14, 2009·7 cites·19 claims
- 2374US7721170B2Apparatus and method for selectively implementing launch off scan capability in at speed testingIBM·Filed 2007·Granted May 18, 2010·7 cites·14 claims
- 2474US5783960AIntegrated circuit device with improved clock signal controlIBM·Filed 1997·Granted Jul 21, 1998·36 cites·16 claims
- 2572US6636995B1Method of automatic latch insertion for testing application specific integrated circuitsIBM·Filed 2000·Granted Oct 21, 2003·17 cites·18 claims
- 2670US8504971B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Aug 6, 2013·2 cites·16 claims
- 2770US7482851B2Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibilityIBM·Filed 2007·Granted Jan 27, 2009·5 cites·11 claims
- 2867US6856270B1Pipeline arrayIBM·Filed 2004·Granted Feb 15, 2005·14 cites·20 claims
- 2965US8205124B2Microcontroller for logic built-in self test (LBIST)GRISE GARY D·Filed 2008·Granted Jun 19, 2012·3 cites·26 claims
- 3065US7484149B2Negative edge flip-flops for muxscan and edge clock compatible LSSDIBM·Filed 2006·Granted Jan 27, 2009·3 cites·1 claims
- 3164US8117579B2LSSD compatibility for GSD unified global clock buffersWARNOCK JAMES DOUGLAS·Filed 2008·Granted Feb 14, 2012·6 cites·13 claims
- 3264US7529294B2Testing of multiple asynchronous logic domainsIBM·Filed 2006·Granted May 5, 2009·4 cites·20 claims
- 3363US7435990B2Arrangement for testing semiconductor chips while incorporated on a semiconductor waferIBM·Filed 2003·Granted Oct 14, 2008·7 cites·5 claims
- 3463US6865723B2Method for insertion of test points into integrated logic circuit designsIBM·Filed 2003·Granted Mar 8, 2005·8 cites·28 claims
- 3562US7131074B2Nested voltage island architectureIBM·Filed 2003·Granted Oct 31, 2006·10 cites·24 claims
- 3660US8423844B2Dense register array for enabling scan out observation of both L1 and L2 latchesGILLIS PAMELA S·Filed 2011·Granted Apr 16, 2013·1 cites·14 claims
- 3759US6467044B1On-board clock-control templates for testing integrated circuitsIBM·Filed 1999·Granted Oct 15, 2002·34 cites·10 claims
- 3856US6804803B2Method for testing integrated logic circuitsIBM·Filed 2001·Granted Oct 12, 2004·5 cites·25 claims
- 3954US6745373B2Method for insertion of test points into integrated circuit logic designsIBM·Filed 2001·Granted Jun 1, 2004·5 cites·20 claims
- 4053US6566681B2Apparatus for assisting backside focused ion beam device modificationIBM·Filed 2001·Granted May 20, 2003·2 cites·8 claims
- 4152US6731154B2Global voltage buffer for voltage islandsIBM·Filed 2002·Granted May 4, 2004·5 cites·7 claims
- 4247US7996739B2Avoiding race conditions at clock domain crossings in an edge based scan designIBM·Filed 2009·Granted Aug 9, 2011·0 cites·24 claims
- 4346US2008270861A1Negative edge flip-flops for muxscan and edge clock compatible lssdLACKEY DAVID E·Filed 2008·Application pending·0 cites
- 4446US2008270863A1Methods of synchronous digital operation and scan based testing of an integrated circuit using negative edge flip-flops for muxscan and edge clock compatible lssdLACKEY DAVID E·Filed 2008·Application pending·0 cites
- 4544US2009150844A1Critical path selection for at-speed testIBM·Filed 2007·Application pending·0 cites
- 4639US7937632B2Design structure and apparatus for a robust embedded interfaceIBM·Filed 2008·Granted May 3, 2011·0 cites·15 claims
- 4737US8181135B2Hold transition fault model and test generation methodIYENGAR VIKRAM·Filed 2009·Granted May 15, 2012·0 cites·15 claims
- 4833US8239715B2Method and apparatus for a robust embedded interfaceEUSTIS STEVEN M·Filed 2008·Granted Aug 7, 2012·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →