Negative edge flip-flops for muxscan and edge clock compatible lssd

Abstract

A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch.

1 . A flip-flop, comprising:
 a master latch having an input and a clock pin;   a slave latch having an output, a first clock pin and a second clock pin, said slave latch connected to said to said master latch;   a first AND gate having a first input, an inverted second input and an output, said output of said first AND gate connected to said first clock pin of said master latch;   a second AND gate having a first input, an inverted second input and an output, said output of said second AND gate connected to said second input of said first AND gate and to said first clock pin of said slave latch.   
   
   
       2 . The flip-flop of  claim 1 , wherein:
 said master latch is adapted to capture data presented at said input of said master latch and to transfer data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch;   said slave latch is adapted to launch data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and   said master latch is adapted to capture data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.   
   
   
       3 . The flip-flop of  claim 2 , wherein said slave latch is further adapted to load data stored in said master latch in response to a third clock signal on said second clock pin of said slave latch. 
   
   
       4 . The flip-flop of  claim 2 , wherein said first clock signal is connected to said second input of said second AND gate and said second clock signal is connected to said first input of said first AND gate. 
   
   
       5 . The flip-flop of  claim 2 , wherein said slave latch is further adapted to load and store data stored in said master latch in response to a fourth clock signal on said first clock pin of said slave latch. 
   
   
       6 . The flip-flop of  claim 5 , wherein said fourth clock signal is connected to said first input of said second AND gate. 
   
   
       7 . The flip-flop of  claim 1 , further including:
 a multiplexer having a first and a second input, a control input and an output, said output of said multiplexer connected to said input of said master latch.   
   
   
       8 . The flip-flop of  claim 7 , wherein:
 said first input of said multiplexer is connected to either a scan-chain input or to an output of another flip-flop; and   said second input of said multiplexer is connected to a logic circuit of an integrated circuit, said flip-flop and said integrated circuit on a same integrated circuit chip.   
   
   
       9 . The flip-flop of  claim 1 , said master latch further including an additional input and an additional clock input. 
   
   
       10 . The flip-flop of  claim 9 , wherein:
 said input of said master latch is connected to either a scan-chain input or to an output of another flip-flop; and   said additional input of said master latch is connected to a logic circuit of an integrated circuit, said flip-flop and said integrated circuit on a same integrated circuit chip.   
   
   
       11 . The flip-flop of  claim 9 , wherein said master latch is adapted to capture data presented at said additional input of said master latch in response to a fifth clock signal on said additional pin of said master latch.