Assignee
LACKEY DAVID E
US·4 granted patents·2 pending applications·14 citations·filing 2007–2012
Top patents by PatentIndex Score
6 records- 0183US8589843B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Nov 19, 2013·4 cites·13 claims
- 0279US8490045B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Jul 16, 2013·3 cites·22 claims
- 0376US8122409B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2007·Granted Feb 21, 2012·5 cites·10 claims
- 0470US8504971B2Method and device for selectively adding timing margin in an integrated circuitLACKEY DAVID E·Filed 2012·Granted Aug 6, 2013·2 cites·16 claims
- 0546US2008270861A1Negative edge flip-flops for muxscan and edge clock compatible lssdLACKEY DAVID E·Filed 2008·Application pending·0 cites
- 0646US2008270863A1Methods of synchronous digital operation and scan based testing of an integrated circuit using negative edge flip-flops for muxscan and edge clock compatible lssdLACKEY DAVID E·Filed 2008·Application pending·0 cites
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