N+ poly on high-k dielectric for semiconductor devices

Abstract

The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region ( 304 ) is formed within a semiconductor body ( 302 ). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region ( 307 ). A high-k dielectric layer ( 308 ) is formed over the device ( 300 ). A polysilicon layer ( 310 ) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer ( 308 ) and the polysilicon layer ( 310 ) are patterned to form polysilicon gate structures. P-type source/drain regions ( 306 ) are formed within the n-type well region ( 304 ).

1 - 16 . (canceled) 
   
   
       17 . A semiconductor device comprising:
 an n-type well region formed within a semiconductor body;   a shallow p-type counter doped region formed within the n-type well region;   a polysilicon gate structure formed on the n-type well region comprised of an n-type doped polysilicon gate formed on a high-k dielectric layer; and   p-type source and drain regions formed within the n-type well region on opposite sides of the polysilicon gate structure.   
   
   
       18 . The semiconductor device of  claim 17 , wherein the shallow p-type counter doped region has a depth and dopant concentration according to a known threshold voltage shift. 
   
   
       19 . The semiconductor device of  claim 17 , wherein the high-k dielectric layer is comprised of HfSiON. 
   
   
       20 . The semiconductor device of  claim 17 , wherein the shallow p-type counter doped region further comprises a diffusion inhibitor. 
   
   
       21 . The semiconductor device of  claim 20 , wherein the diffusion inhibitor is silicon carbide.