US2008283941A1PendingUtilityA1

Fabrication of transistors with a fully silicided gate electrode and channel strain

49
Assignee: TEXAS INSTRUMENTS INCPriority: Feb 14, 2007Filed: Jul 15, 2008Published: Nov 20, 2008
Est. expiryFeb 14, 2027(~0.6 yrs left)· nominal 20-yr term from priority
H10D 64/0132H10D 62/822H10D 84/0174H10D 84/0167H10D 64/017H10D 62/021H10D 30/797H10D 84/038H10D 84/017
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit, comprising:
 one or more transistors on or in a semiconductor substrate, wherein at least one of said transistors includes:
 a gate having a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to 3:1; and 
 source and drain structures located in openings of said substrate and adjacent to said gate, wherein said source and drain structures are filled with SiGe. 
   
   
   
       2 . The circuit of  claim 1 , wherein said ratio equals about 2:1 at an interface of said fully silicided gate electrode layer and an underlying gate dielectric layer. 
   
   
       3 . The circuit of  claim 1 , wherein said ratio equals about 3:1 at an interface of said fully silicided gate electrode layer and an underlying gate dielectric layer. 
   
   
       4 . The circuit of  claim 1 , further including a second transistor including:
 a second gate having a fully silicided second gate electrode layer, wherein a second interface of said fully silicided second gate electrode layer and an underlying second dielectric layer has a second ratio of Ni:Si ranging from about to 1.1:1; and   second source and drain structures in said substrate and adjacent to said second gate, wherein said source and drain structures are free of SiGe.   
   
   
       5 . The circuit of  claim 4 , wherein said second ratio increases from said second interface to an upper surface of said second gate.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.