Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers

Abstract

Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

1 . A silicon space transformer package structure, comprising:
 a planar silicon substrate having a thickness of less than about 150 microns between first ana second opposing planar surfaces;   a plurality of conductive through-vias formed in the planar silicon substrate to provide vertical electrical connections extending through the silicon substrate between the first and second opposing planar surfaces;   a wiring layer formed on the first planar surface of the silicon substrate, the first wiring layer comprising a first pattern of electrical contacts and integrated circuit components and redistribution wiring;   a second pattern of electrical contacts formed on the second surface of the silicon substrate   wherein the redistribution wiring and conductive-through vias provide space transform electrical connections between the first pattern and second pattern of electrical contacts.   
     
     
         2 . The silicon space transformer package structure of  claim 1 , wherein the first pattern of electrical contacts is an area array of contacts having a pitch P 1  and wherein the second pattern of electrical contacts is an area array of contacts having a pitch P 2 , where P 2 >P 1 . 
     
     
         3 . The silicon space transformer package structure of  claim 1 , wherein the first pattern of electrical contacts is a perimeter array of contacts having a pitch P 1  and wherein the second pattern of electrical contacts is an area array of contacts having a pitch P 2 , where P 2 >P 1 . 
     
     
         4 . The silicon space transformer package structure of  claim 1 , further comprising a plurality of passive devices formed on the first planar surface of the silicone substrate and electrically connected to the wiring layer. 
     
     
         5 . The silicon space transformer package structure  claim 1 , wherein the wiring layer is a multilayer structure comprising three or more metallization levels. 
     
     
         6 . The silicon space transformer package structure of  claim 5 , wherein the wiring layer comprise power and ground wiring levels. 
     
     
         7 . The silicon space transformer package structure of  claim 1 , wherein the planar silicon substrate comprises an open cavity formed therein between the first and second opposing surfaces. 
     
     
         8 . The silicon space transformer package structure of  claim 1 , further comprising:
 a second planar silicon substrate having a thickness of less than about 150 microns between first and second opposing planar surfaces thereof;   a plurality of conductive through-vias formed in the second planar silicon substrate to provide vertical electrical connections extending through the second silicon substrate between the first and second opposing planar surfaces thereof   a wiring layer formed on the first planar surface of the second silicon substrate, the wiring layer comprising a third pattern of electrical contacts and redistribution wiring;   a fourth pattern of electrical contacts formed on the second surface of the second silicon substrate,   wherein the first and second planar silicon substrates are mechanically bonded together with electrical contacts between the second pattern of electrical contacts on the second surface of the first silicon substrate and the third pattern of electrical contacts on the first surface of the second silicon substrate.   
     
     
         9 . The silicon space transformer package structure of  claim 8 , wherein the second silicon substrate provides a space transformation between the second pattern of electrical contacts and the fourth pattern of electrical contacts. 
     
     
         10 . An electronic apparatus, comprising:
 a first level package structure comprising a silicon space transformer chip carrier structure and an IC (integrated circuit) chip flip chip mounted on a first surface of the silicon space transformer chip carrier structure using an first pattern of electrical contacts with pitch P 1 ; and   a second level package substrate comprising a second pattern of electrical contacts with pitch P 2 , wherein P 2 >P 1 , formed on a mounting surface thereof,   wherein the first level package structure is mounted to the mounting surface of the second level package substrate with the silicon space transformer chip carrier structure providing space transforming electrical interconnections between the first pattern of electrical contacts and the second pattern of electrical contacts on the mounting surface of the second level package structure.   
     
     
         11 . The electronic apparatus of  claim 10 , wherein the silicon space transformer chip carrier structure comprises:
 a first planar silicon substrate having a thickness of less than about 150 microns between first and second opposing planar surfaces;   a plurality of conductive through-vias formed in the first planar silicon substrate to provide vertical electrical connections extending through the first silicon substrate between the first and second opposing planar surfaces;   a wiring layer formed on the first planar surface of the silicon substrate, the first wiring layer comprising the first pattern of electrical contacts and redistribution wiring;   wherein the redistribution wiring and conductive-through vias provide space transform electrical connections between the first pattern and second pattern of electrical contacts.   
     
     
         12 . The electronic apparatus of  claim 10 , wherein the first pattern of electrical contacts is an area array of contacts having a pitch P 1  and wherein the second pattern of electrical contacts is an area array of contacts having a pitch P 2 , where P 2 >P 1 . 
     
     
         13 . The electronic apparatus of  claim 10 , wherein the first pattern of electrical contacts is a perimeter array of contacts having a pitch P 1  and wherein the second pattern of electrical contacts is an area array of contacts having a pitch F 2 , where P 2 >P 1 . 
     
     
         14 . The electronic apparatus of  claim 10 , further comprising a plurality of passive devices formed on the first planar surface of the first silicone substrate and electrically connected to the wiring layer. 
     
     
         15 . The electronic apparatus of  claim 10 , wherein the wiring layer is a multilayer structure comprising three or more metallization levels. 
     
     
         16 . The electronic apparatus of  claim 15 , wherein the wiring layer comprise power and ground wiring levels. 
     
     
         17 . The electronic apparatus of  claim 10 , wherein the planar silicon substrate comprises an open cavity formed therein between the first surface thereof and the mounting surface of the second level package substrate and an electronic device disposed in the open cavity and mounted on the second level package substrate. 
     
     
         18 . The electronic apparatus of  claim 10 , wherein the silicon space transformer carrier structure comprises a stack of two or more planar silicon substrates each having a thickness of less than about 150 microns to about 1-10 um. 
     
     
         19 . The electronic apparatus of  claim 10 , wherein the first pattern of electrical contacts of the silicon space transformer carrier structure provide an array of pads for interconnection to one or more integrated circuit (IC) chips with I/O interconnection densities greater than about 500 I/O per mm 2 . 
     
     
         20 . The electronic apparatus of  claim 19 , wherein the I/O interconnection densities are greater than about 1000 I/O per mm 2 . 
     
     
         21 . The electronic chips apparatus of  claim 19 , wherein the one or more IC chips include a memory chip, a chip stack, a processor chip, a graphics chip, a game chip, an image sensing chip or a combination of such chips, which are separately mounted on the silicon space transformer carrier structure or mounted in a stacked configuration on the silicon space transformer carrier structure. 
     
     
         22 . The electronic apparatus of  claim 18 , wherein each of the planar silicon substrates have conductive through-vias formed therein to provide vertical electrical connections extending between top and bottom sides of the stack of planar silicone substrates. 
     
     
         23 . A method for fabricating a semiconductor package structure, comprising:
 providing a silicon substrate having a thickness t 1  between first and second opposing planar surfaces;   forming a pattern of conductive vias to a depth d below the first surface of silicon substrate, which is less than the thickness t 1  of the silicon substrate;   forming a wiring layer on the first surface of the silicon substrate, wherein the wiring layer comprises a first pattern of electrical contacts and redistribution wiring that provides electrical connections between the first pattern of electrical contacts and the conductive vias;   bonding a glass handler substrate to the wiring layer on the first surface of the silicon substrate;   recessing the second surface of the silicon substrate to expose bottom portions of the blind conductive vias and reduce the thickness t 1  of the silicone substrate to a thickness t 1 ′, where t 1 ′ is less than about 150 microns to about 1-10 um;   forming an insulating layer on the recessed second surface of the silicon substrate with the bottom portions of the conductive vias exposed; and   forming electrical contacts on the exposed bottom portions of the conductive vias to provide a second pattern of electrical contacts;   bonding the second pattern of electrical contacts to a third pattern of electrical contacts on a second package substrate layer; and   removing the mechanical glass handler substrate.   
     
     
         24 . The method of  claim 23 , wherein the second package substrate layer comprises an organic laminate substrate. 
     
     
         25 . The method of  claim 24 , further comprising etching an open cavity through the silicon substrate from the recessed second surface to the first surface thereof prior to bonding the second pattern of electrical contacts to the third pattern of electrical contacts on the second package substrate layer. 
     
     
         26 . The method of  claim 23 , wherein the second package substrate layer comprises a second silicon substrate having a thickness t 2  between first and second opposing planar surfaces and a second pattern of conductive vias formed to a depth d 2  below the first surface of second silicon substrate, which is less than the thickness t 2  of the second silicon substrate, wherein the third pattern of electrical contacts are electrically connected to exposed end portions of respective conductive vias in the second pattern of conductive vias, the method further comprising:
 prior to removing the glass handler substrate;   recessing the second surface of the second silicon substrate to expose bottom portions of the second pattern of conductive vias and reduce the thickness t 2  of the second silicone substrate to a thickness t 2 ′, where t 2 ′ is less than about 150 microns to about 1-10 um;   forming an insulating layer on the recessed second surface of the second silicon substrate with the bottom portions of the second pattern of conductive vias exposed; and   forming electrical contacts on the exposed bottom portions of the conductive vias to provide a further pattern of electrical contacts.   
     
     
         27 . The method of  claim 26 , wherein prior to bonding the second pattern of electrical contacts to the third pattern of electrical contacts on the second package substrate layer, the method further comprising:
 etching an open cavity through the silicon substrate from the recessed second surface to the first surface thereof;   etching a closed end cavity in the first surface of the second silicon substrate down to a depth below the depth d 2  of the second pattern of conductive vias;   aligning the open cavity and closed end cavity when bonding the first and second silicon substrates; and   opening the closed end cavity during recessing the second surface of the second silicon substrate.   
     
     
         28 . The method of  claim 23 , wherein forming a pattern of conductive vias in the first surface of the first silicon substrate comprises:
 etching a pattern of annular trenches in the first surface of the first silicone substrate to the depth d 1  below the first surface of the substrate, each annular trench surrounding an inner core of silicon substrate material;   forming a liner layer on the exposed sidewall surfaces of the annular trenches and   filling the annular trenches with a metallic material.