Circuit and method for a three dimensional non-volatile memory

Abstract

An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

1 . A nonvolatile memory cell, comprising:
 a uniformly doped silicon region having a source region, a channel region, and a drain region;   a charge trapping storage dielectric overlying the channel region; and   a conductive gate region overlying the charge trapping dielectric region.   
     
     
         2 . The non-volatile memory cell of  claim 1 , wherein a read of the memory cell determines whether current flows in response to a predetermined potential on the gate region. 
     
     
         3 . The non-volatile memory cell of  claim 1 , wherein the uniformly doped silicon region is an epitaxial silicon region. 
     
     
         4 . The non-volatile memory cell of  claim 1 , wherein the source region, the channel region, and the drain region having a same type dopant. 
     
     
         5 . The non-volatile memory cell of  claim 1 , and further comprising:
 providing the charge trapping storage dielectric comprising an oxide, a nitride overlying the oxide, and an oxide overlying the nitride.   
     
     
         6 . The non-volatile memory cell of  claim 1 , wherein the charge trapping dielectric overlies the uniformly doped silicon region on three sides, and the conductive gate region overlies the charge trapping dielectric, so that non-volatile memory cell forms a FinFET device. 
     
     
         7 . The non-volatile memory cell of  claim 2 , wherein the conductive gate region, charge trapping storage dielectric, and uniformly doped silicon region form a fully depleted silicon over insulator (FD-SOI) device. 
     
     
         8 . A plurality of non volatile memory cells, comprising:
 a uniformly doped silicon region;   a plurality of cell regions formed apart one from another in the uniformly doped silicon region, each cell region comprising a source region, a drain region, and a channel region between the source and drain regions;   charge trapping storage regions overlying each of the channel regions; and   a plurality of gate electrodes overlying each of the cell regions, each gate electrode overlying a charge trapping storage region.   
     
     
         9 . The plurality of non-volatile memory cells of  claim 8 , wherein the cells are coupled together to form a NAND memory array. 
     
     
         10 . The plurality of non-volatile memory cells of  claim 8 , and further comprising a source select transistor coupled between a global bit line and the uniformly doped silicon region for inputting and outputting data to the non-volatile memory cells. 
     
     
         11 . The plurality of non-volatile memory cells of  claim 8 , and further comprising a ground select transistor coupled between a voltage source and the uniformly doped silicon region for selectively providing a path from the array of non-volatile memory cells to the voltage source. 
     
     
         12 . The plurality of non-volatile memory cells of  claim 8 , wherein the uniformly doped silicon region further comprises an epitaxial silicon region. 
     
     
         13 . A three dimensional array of non-volatile memory storage cells, comprising:
 a substrate;   one or more memory layers overlying the substrate, each comprising:
 a uniformly doped silicon region having a plurality of spaced apart memory cell regions formed within it, each memory cell region comprising a source region, a drain region and a channel region between the source and drain regions; 
 charge trapping storage dielectrics formed over each of the memory cell regions and overlying the channel region; 
 conductive gate electrodes formed overlying the charge trapping storage dielectric for each of the memory cell regions; 
 a dielectric layer overlying the gate electrodes and separating the respective memory layers in a vertical direction. 
   
     
     
         14 . The array of memory storage cells in  claim 13 , and further comprising:
 at least one MOS device formed in the silicon substrate; and   a contact extending from the first memory layer through the insulating layer.   
     
     
         15 . The array of storage cells in  claim 13 , and further comprising:
 at least one via formed in an interlevel dielectric layer between two of the memory layers.   
     
     
         16 . The array of storage cells in  claim 13 , wherein each of the silicon regions forms a local bit line and the memory cell regions are coupled in series to form a NAND memory array within the memory layer. 
     
     
         17 . The array of storage cells in  claim 13 , wherein each of the gate electrodes is coupled to a word line and a memory cell is located at the intersections of the word lines and the local bit lines. 
     
     
         18 . The array of storage cells in  claim 13 , wherein each of the storage cells is a silicon oxide nitride oxide silicon (SONOS) cell. 
     
     
         19 . The array of storage cells in  claim 18 , wherein each of the storage cells is a fully depleted silicon over insulator (FD-SOI) device. 
     
     
         20 . The array of storage cells in  claim 18 , wherein each of the storage cells is a FinFET device.