Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors

Abstract

Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

1 . A bonded structure comprising:
 a first structure;   a second structure; and   a low temperature grown semiconductor bonding layer between the first and second structures and comprising at least one of an amorphous and a polycrystalline semiconductor material, the semiconductor material including at least one column III element and at least one column V element, wherein an atomic ratio of the column V element to the column III element is not equal to 1.   
   
   
       2 . The bonded structure of  claim 1  wherein the semiconductor material includes an excess of the column V element, the atomic ratio of the column V element to the column III element being greater than 1. 
   
   
       3 . The bonded structure of  claim 1  wherein the semiconductor material includes an excess of the column III element, the atomic ratio of the column V element to the column III element being less than 1. 
   
   
       4 . The bonded structure of  claim 1  wherein the column III element is selected from the group consisting of Ga and In. 
   
   
       5 . The bonded structure of  claim 1  wherein the column V element is selected from the group consisting of As, N, P and Sb. 
   
   
       6 . The bonded structure of  claim 1  wherein the semiconductor material includes two column III elements. 
   
   
       7 . The bonded structure of  claim 1  wherein the semiconductor material includes two column V elements. 
   
   
       8 . The bonded structure of  claim 1  wherein the bonding layer comprises at least one compound semiconductor. 
   
   
       9 . The bonded structure of  claim 1  wherein the bonding layer comprises a dopant. 
   
   
       10 . The bonded structure of  claim 9  wherein the dopant is silicon. 
   
   
       11 . The bonded structure of  claim 1  wherein the bonding layer does not include an amorphous semiconductor material. 
   
   
       12 . The bonded structure of  claim 1  wherein the bonding layer includes an amorphous sublayer sandwiched between two polycrystalline sublayers. 
   
   
       13 . The bonded structure of  claim 1  wherein the bonding layer has a thickness of from about 3 nm to about 600 nm. 
   
   
       14 . The bonded structure of  claim 1  wherein the first structure has a misalignment angle with respect to the second structure. 
   
   
       15 . The bonded structure of  claim 14  wherein the misalignment angle is in the range of from 2 degrees to 40 degrees. 
   
   
       16 . The bonded structure of  claim 1  wherein at least one of the first and second structures comprises a semiconductor substrate. 
   
   
       17 . The bonded structure of  claim 1  wherein a layer comprising a semiconductor material is disposed between the bonding layer and at least one of the first and second structures. 
   
   
       18 . A bonded structure for an electronic device comprising:
 a first structure;   a second structure; and   a low temperature grown semiconductor bonding layer bonding the first and second structures and including at least one of an amorphous and a polycrystalline semiconductor material, the semiconductor material including Ga and at least one element selected from the group consisting of As, P, and N.   
   
   
       19 . The bonded structure of  claim 18  wherein an atomic ratio of the element to the Ga is equal to 1. 
   
   
       20 . The bonded structure of  claim 18  wherein an atomic ratio of the element to the Ga is not equal to 1. 
   
   
       21 . The bonded structure of  claim 20  wherein the semiconductor material includes an excess of the element, the atomic ratio of the element to the Ga being greater than 1. 
   
   
       22 . The bonded structure of  claim 20  wherein the semiconductor material includes an excess of the Ga, the atomic ratio of the element to the Ga being less than 1. 
   
   
       23 . The bonded structure of  claim 18  wherein the electronic device is selected from the group consisting of a photodiode, transistor, light-emitting diode, and laser. 
   
   
       24 . A method of fabricating an electronic device, the method comprising:
 depositing low temperature grown semiconductor bonding layers on first and second structures wherein at least one of the bonding layers comprises a column III element and column V element, and further wherein at least one of the bonding layers comprises an amorphous material;   placing the bonding layers in contact with each other to form a combined structure;   applying pressure to the combined structure; and   crystallizing at least a portion of the amorphous material of the bonding layers to a polycrystalline material during the application of pressure to bond the first and second structures together and form a bonded combined structure, and   processing the bonded combined structure to form an electronic device.   
   
   
       25 . The method of  claim 24  wherein the electronic device is selected from the group consisting of a photodiode, transistor, light-emitting diode, and laser. 
   
   
       26 . The method of  claim 25  wherein the transistor is one of a heterojunction bipolar transistor and a high-electron-mobility transistor.