Highly Scalable Thin Film Transistor

Abstract

Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

1 . A monolithic three dimensional array comprising:
 a) a first device level monolithically formed above a substrate, the first device level comprising a first plurality of field effect transistors, each of the first plurality of field effect transistors having source, drain, and channel regions comprising polycrystalline silicon-germanium, wherein the source and drain regions are doped with a p-type dopant; and   b) a second device level monolithically formed above the first device level;   wherein:   each of the first plurality of field effect transistors further comprises a control gate, an oxide layer located between the channel region and the gate electrode, and a high-k dielectric layer on and in contact with the oxide layer; and   the high-k dielectric layer has a dielectric constant greater than  8 .   
     
     
         2 . The monolithic three dimensional array of  claim 1 , wherein the substrate comprises monocrystalline silicon. 
     
     
         3 . The monolithic three dimensional array of  claim 1 , wherein each of the first plurality of field effect transistors is a memory cell comprising a charge storage region. 
     
     
         4 . (canceled) 
     
     
         5 . The monolithic three dimensional array of  claim 1 , wherein the gate electrode of each of the first plurality of field effect transistors is doped with a p-type dopant. 
     
     
         6 . The monolithic three dimensional array of  claim 1 , wherein the polycrystalline silicon-germanium layer is Si x Ge 1-x , and wherein x is between about 0.6 and about 0.9. 
     
     
         7 . The monolithic three dimensional array of  claim 6 , wherein x is between about 0.75 and about 0.85. 
     
     
         8 . The monolithic three dimensional array of  claim 1 , wherein the high-k dielectric layer comprises HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, or ZrSiAlON. 
     
     
         9 . A method for forming a monolithic three dimensional device, the method comprising:
 depositing a first semiconductor material layer above a substrate, wherein the first semiconductor material layer is amorphous as deposited and comprises silicon-germanium alloy;   forming a first plurality of field effect transistors, each first field effect transistor having a first channel region comprising a portion of the first layer of semiconductor material;   depositing a second semiconductor material layer above the first field effect transistors, wherein, when the second semiconductor material layer is deposited, the first layer of semiconductor material remains predominantly amorphous; and   forming a second plurality of field effect transistors, each second field effect transistor having a second channel region comprising a portion of the second layer of semiconductor material;   wherein:   the step of forming the first plurality of field effect transistors comprises growing an oxide layer between the first channel region and a gate electrode of the first plurality of field effect transistors transistor, and depositing a high-k dielectric layer having a dielectric constant greater than 8 on and in contact with the oxide layer.   
     
     
         10 . The method of  claim 9 , wherein the semiconductor material is Si x Ge 1-x , and wherein x is between about 0.6 and about 0.9. 
     
     
         11 . The method of  claim 10 , wherein x is between about 0.75 and about 0.85. 
     
     
         12 . The method of  claim 9 , wherein each of the first plurality of field effect transistors or each of the second plurality of field effect transistors is a PMOS transistor. 
     
     
         13 . The method of  claim 9 , further comprising an annealing step after the step of forming the second plurality of field effect transistors, the annealing step comprising:
 a first annealing stage performed at between about 450 and about 650° C. for at least thirty minutes; and   a second annealing stage performed at between about 650 and about 800° C. for no more than 120 seconds.   
     
     
         14 . The method of  claim 13 , wherein the first annealing stage lasts for about one hour to about 24 hours. 
     
     
         15 . The method of  claim 9 , wherein each of the first plurality of field effect transistors is a memory cell comprising a charge storage region. 
     
     
         16 . The method of  claim 15 , wherein the charge storage region comprises at least two oxides. 
     
     
         17 . The method of  claim 9 , the step of growing an oxide layer comprises growing an oxide layer at a temperature less than or about 560° C. by oxidizing part of the first silicon-germanium semiconductor material layer. 
     
     
         18 . The method of  claim 9 , wherein the high-k dielectric layer comprises HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, or ZrSiAlON. 
     
     
         19 . The method of  claim 9 , wherein the oxide layer has a thickness of 20 angstroms or less. 
     
     
         20 . The method of  claim 9 , wherein the substrate comprises monocrystalline silicon. 
     
     
         21 . A method for forming a monolithic three dimensional device, the method comprising:
 depositing a first layer of semiconductor material above a substrate, wherein the first layer of semiconductor material is amorphous as deposited;   forming a first plurality of field effect transistors, each first field effect transistor having a channel region comprising a portion of the first layer of semiconductor material;   depositing a second layer of semiconductor material above the first field effect transistors, wherein, when the second layer of semiconductor material is deposited, the first layer of semiconductor material remains predominantly amorphous;   forming a second plurality of field effect transistors, each second field effect transistor having a channel region comprising a portion of the second layer of semiconductor material; and   recrystallizing the first and second layers of semiconductor material from amorphous form to polycrystalline form.   
     
     
         22 . The method of  claim 21 , wherein the step of recrystallizing the first and second layers of semiconductor material comprises thermally annealing the first and second layers of semiconductor material.