Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device

Abstract

A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

1 . A semiconductor memory device comprising:
 a memory cell array storing data;   a plurality of address pads used to designate the memory cell array;   a plurality of data input/output pads for reading data from and writing data to the memory cell array, the plurality of data input/output pads divided into a plurality of data input/output groups during a test mode for the memory cell array; and   a control signal generation pad capable of writing non-identical data to the plurality of data input/output pads of each group when data is written to the memory cell array during the test mode.   
   
   
       2 . The semiconductor memory device of  claim 1 , further comprising a data input multiplexer (DINMUX) coupled to the control signal generation pad. 
   
   
       3 . The semiconductor memory device of  claim 2 , wherein the data input multiplexer (DINMUX) controls designation of the plurality of data input/output pads according to the frequency of toggling of a control signal. 
   
   
       4 . The semiconductor memory device of  claim 1 , wherein the control signal generation pad is a control pin not used in the test mode for the memory cell array. 
   
   
       5 . The semiconductor memory device of  claim 1 , wherein the plurality of data input/output pads of each group are connected to one input/output (I/O) channel of a tester when the memory cell array is tested. 
   
   
       6 . The semiconductor memory device of  claim 1 , wherein the device comprises 2N (N is a natural number) data input/output pads in each group of the plurality of data input/output pads. 
   
   
       7 . The semiconductor memory device of  claim 1 , wherein the test mode for the memory cell array is a mode for a writing function of 2 m (m is a natural number) memory cells. 
   
   
       8 . The semiconductor memory device of  claim 1 , wherein the test mode for the memory cell array is included in an electrical die sort (EDS) test. 
   
   
       9 . The semiconductor memory device of  claim 1 , wherein the test mode for the memory cell array is included in a final electrical test.