Semiconductor storage device and read voltage correction method

Abstract

A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.

1 . A semiconductor storage device comprising:
 a semiconductor memory;   a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage set by a reference semiconductor memory of the semiconductor memory; and   a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.   
     
     
         2 . The device according to  claim 1 , further comprising an interconnect line which electrically connect the corrected voltage storage circuit to the controller, and wherein, in a read operation, the corrected voltage is read from the corrected voltage storage circuit over the interconnect line by the memory controller. 
     
     
         3 . The device according to  claim 1 , wherein the corrected voltage storage circuit includes a memory cell to store the corrected voltage. 
     
     
         4 . The device according to  claim 3 , wherein the memory cell is a memory cell transistor which has its current path electrically connected at one end to the memory controller. 
     
     
         5 . The device according to  claim 3 , wherein the memory cell is a ferroelectric memory transistor which has its current path electrically connected at one end to the memory controller. 
     
     
         6 . The device according to  claim 1 , wherein the corrected voltage storage circuit is placed in a peripheral circuit of the semiconductor memory. 
     
     
         7 . The device according to  claim 1 , wherein the semiconductor memory has a memory cell array, a row decoder, a sense amplifier, and a source line driver. 
     
     
         8 . The device according to  claim 7 , wherein the memory cell array has a plurality of memory cells arranged in the form of a matrix at intersections of word lines and bit lines, and the controller controls the memory cell array so that, in a read operation, the corrected voltage is applied to nonselected memory cells and a predetermined voltage is applied to a selected memory cell. 
     
     
         9 . The device according to  claim 1 , wherein the semiconductor memory is a NAND type flash memory. 
     
     
         10 . The device according to  claim 1 , wherein, when the storage device is taken as a to-be-corrected semiconductor memory the read voltage of which is to be corrected by referring to the reference semiconductor memory, the corrected voltage is given by
   (Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ′÷Cγ)}   
       wherein Cγ′ is the coupling ratio of the corrected semiconductor memory, Cγ is the coupling ratio of the reference semiconductor memory, Vread is the read voltage of the corrected semiconductor memory before correction, Vt is the threshold voltage of memory cells of the reference semiconductor memory, and Vt 0  is the neutral threshold voltage of the memory cells of the reference semiconductor memory. 
     
     
         11 . The device according to  claim 9 , wherein, when the storage device is taken as a to-be-corrected semiconductor memory the read voltage of which is to be corrected by referring to the reference semiconductor memory, the corrected voltage is given by
   (Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ÷Cγ)}   
       wherein Cγ′ is the coupling ratio of the corrected semiconductor memory, Cγ is the coupling ratio of the reference semiconductor memory, Vread is the read voltage of the corrected semiconductor memory before correction, Vt is the threshold voltage of memory cells of the reference semiconductor memory, and Vt 0  is the neutral threshold voltage of the memory cells of the reference semiconductor memory. 
     
     
         12 . The device according to  claim 1 , wherein the semiconductor memory and the reference semiconductor memory are formed on a same wafer. 
     
     
         13 . The device according to  claim 10 , wherein the coupling ratio of the reference semiconductor memory, the threshold voltage of memory cells of the reference semiconductor memory, and the neutral threshold voltage of the memory cells of the reference semiconductor memory, are obtained by measuring TEG. 
     
     
         14 . A read voltage correction method for use with a semiconductor storage device equipped with a reference semiconductor memory and a to-be-corrected semiconductor memory which has a corrected voltage storage circuit, comprising:
 obtaining a write voltage of the to-be-corrected semiconductor memory;   obtaining an erase voltage of the to-be-corrected semiconductor memory; and   correcting a read voltage of the to-be-corrected semiconductor memory in accordance with the write and erase voltages obtained.   
     
     
         15 . The method according to  claim 14 , further comprising storing the corrected read voltage into the corrected voltage storage circuit of the to-be-corrected semiconductor memory. 
     
     
         16 . The method according to  claim 14 , wherein the corrected read voltage is given by
   (Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ÷Cγ)}   
       wherein Cγ′ is the coupling ratio of the to-be-corrected semiconductor memory, Cγ is the coupling ratio of the reference chip, Vread is the read voltage of the to-be-corrected semiconductor memory before correction, Vt is the threshold voltage of memory cells of the reference semiconductor memory, and Vt 0  is the neutral threshold voltage of the memory cells of the reference semiconductor memory. 
     
     
         17 . The method according to  claim 14 , wherein the floating gate potential Vfg of the reference semiconductor memory is expressed by
   Vfg=Cγ(Vcg−Vth+Vt0)   
       where Vcg is the gate potential of the reference semiconductor memory, and Vth is the cell threshold potential. 
     
     
         18 . The method according to  claim 14 , wherein the floating gate potential Vfg′ of the to-be-corrected semiconductor memory is expressed by
   Vfg′=Cγ′(Vcg′−Vth+Vt0′)   
       where Cγ′ is the coupling ratio of the to-be-corrected semiconductor memory, Vcg′ is the gate potential of the to-be-corrected semiconductor memory, Vth is the cell threshold potential, and Vt 0 ′ is the cell neutral threshold of the to-be-corrected semiconductor memory. 
     
     
         19 . The method according to  claim 14 , wherein values necessary for the correction method are detected by a probe which is electrically connected to the reference semiconductor memory or the to-be-corrected semiconductor memory and then processed and displayed by a tester. 
     
     
         20 . The method according to  claim 19 , wherein an examination of read disturb characteristic is added to examinations of electric characteristics prior to dicing.