Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of fabricating the same

Abstract

A semiconductor chip having a solder bump and a method of fabricating the same are provided. Conventionally, an inter-metallic compound (IMC) unexpectedly grows at an interface of the solder bump by means of heat generated during operation of the semiconductor chip, thereby weakening mechanical property of the semiconductor chip. To solve this drawback, the semiconductor chip includes at least one metal adhesion layer formed on an electrode pad of the semiconductor chip, an interlayer isolation layer formed on the metal adhesion layer, at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump, and the solder bump formed on the penetration layer. Thereby, materials of the penetration layer penetrate into the solder bump to change the solder bump into a multi-component solder bump, so that the growth of the IMC is suppressed, and the reliability of the semiconductor chip can be improved.

1 . A semiconductor chip having a solder bump, comprising:
 at least one metal adhesion layer formed on an electrode pad of the semiconductor chip;   an interlayer isolation layer formed on the metal adhesion layer;   at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump; and   the solder bump formed on the penetration layer.   
   
   
       2 . The semiconductor chip according to  claim 1 , wherein among the metal adhesion layers, a first metal adhesion layer is formed of at least one of titan (Ti), Ti alloy, aluminum (Al), Al alloy, nickel (Ni), Ni alloy, copper (Cu), Cu alloy, chromium (Cr), Cr alloy, gold (Au), and Au alloy, 
   
   
       3 . The semiconductor chip according to  claim 1 , wherein among the metal adhesion layers, a second metal adhesion layer is formed as needed, and is formed of at least one of Ni, Ni alloy, Cu, Cu alloy, palladium (Pd), and Pd alloy. 
   
   
       4 . The semiconductor chip according to  claim 1 , wherein the interlayer isolation layer is formed of one of Ni, Ni alloy, Pd, and Pd alloy. 
   
   
       5 . The semiconductor chip according to  claim 1 , wherein the penetration layer is formed of at least one of Cu, Cu alloy, antimony (Sb), Sb alloy, indium (In), In alloy, tin (Sn), Sn alloy, bismuth (Bi), Bi alloy, platinum (Pt), Pt alloy, gold (Au) and Au alloy. 
   
   
       6 . The semiconductor chip according to  claim 1 , wherein the penetration layer forms 0.1 to 10% by weight of the solder bump by controlling the thickness or the volume ratio of the penetration layer. 
   
   
       7 . The semiconductor chip according to  claim 1 , wherein the solder bump is formed of one of Au, a lead (Pb)-free solder selected from one of Sn, Sn/Ag, Sn/Cu, Sn/Zn, Sn/Zn/Bi, Sn/Ag/Cu, and Sn/Ag/Bi, and a Pb solder selected from one of high Pb solder and eutectic Pb solder. 
   
   
       8 . A method of fabricating a semiconductor chip having a solder bump, the method comprising the steps of:
 forming at least one metal adhesion layer on an electrode pad of the semiconductor chip;   forming an interlayer isolation layer on the metal adhesion layer;   forming at least one penetration layer on the interlayer isolation layer so as to penetrate into the solder bump when the solder bump is formed; and   forming the solder bump on the penetration layer.   
   
   
       9 . The method according to  claim 8 , further comprising the step of, after the metal adhesion layer is formed, forming photoresist patterns on opposite ends of a top surface of the metal adhesion layer,
 wherein the interlayer isolation layer is formed on the metal adhesion layer between the photoresist patterns.   
   
   
       10 . The method according to  claim 8 , wherein the step of forming the interlayer isolation layer is performed by a sputtering or plating process. 
   
   
       11 . The method according to  claim 8 , wherein the step of forming the penetration layer is performed by a sputtering or plating process. 
   
   
       12 . The method according to  claim 8 , further comprising the step of reflowing the solder bump.