Operating method of non-volatile memory device

Abstract

An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.

1 . An operating method for a non-volatile memory device, applicable on a non-volatile memory device comprising a substrate comprising a trench therein, a first conductive type first well region disposed in the substrate, a second conductive type second well region disposed above the first conductive type first well region, wherein a junction of the first conductive type first well region and the second conductive type second well region is higher than a bottom of the trench, a control gate disposed at a sidewall of the trench, a charge storage layer disposed between the control gate and the substrate, a source region disposed in the substrate at a bottom of the trench beside the control gate, a drain region disposed in the second conductive type second well region beside another side of the control gate, wherein the drain region and the second conductive type second well region are electrically shorted, the operating method comprising:
 applying a first voltage to the control gate, a second voltage to the drain region, a third voltage to the source region and using channel F-N tunneling effect to program the memory cell.   
   
   
       2 . The operating method of  claim 1 , wherein the first voltage is bout −10 volts, the second voltage is about 6 volts and the third voltage is about 6 volts. 
   
   
       3 . The operating method of  claim 1 , further comprising:
 applying a fourth voltage to the control gate, applying a fifth voltage to the source region, applying a sixth voltage to the drain region to read the memory cell.   
   
   
       4 . The operating method of  claim 3 , wherein the fourth voltage is about 3.3 volt, the fifth voltage is about 1.65 volts, and the sixth voltage is about 0 volt. 
   
   
       5 . The operating method of  claim 1 , further comprising:
 applying a seventh voltage to the control gate, setting the drain region at floating, applying an eighth voltage to the source region, applying a ninth voltage to the substrate and using channel F-N tunneling effect to erase the memory cell.   
   
   
       6 . The operating method of  claim 5 , wherein the seventh voltage is about 10 volts, the eighth voltage is about −6 volts, the ninth voltage is about −6 volts.