Manufacturing method of nonvolatile memory

Abstract

A manufacturing method for a non-volatile memory includes first providing a substrate with a gate structure formed thereon. The gate structure includes a first gate and a gate dielectric layer located between the first gate and the substrate. A first doping and a second doping region are formed on the substrate at two sides of the gate, respectively. A first insulating layer is formed on the substrate, and a portion of the first insulating layer and a portion of the substrate are removed to form a trench, which divides the second doping region into a third doping region and a fourth doping region. Finally, a tunneling dielectric layer, a charge-trapping layer and a top dielectric layer are formed inside the trench, and a second gate which fills the trench is formed on the substrate.

1 . A method of manufacturing a non-volatile memory, the method comprising:
 providing a substrate with a gate structure formed thereon, and the gate structure comprises a first gate and a gate dielectric layer disposed between the first gate and the substrate;   forming a first doping region and a second doping region on the substrate at two sides of the first gate;   forming a first insulating layer on the substrate;   removing a portion of the first insulating layer and a portion of the substrate to form a trench, the trench dividing the second doping region into a third doping region and a fourth doping region;   forming a tunneling dielectric layer, a charge-trapping layer and a top dielectric layer in the trench; and   forming a second gate on the substrate to fill the trench.   
     
     
         2 . The method of  claim 1 , the method further comprising:
 forming a second insulating layer on the substrate; and   forming a bite line contact in the second insulating layer electrically connected to the first doping region.   
     
     
         3 . The method of  claim 1 , wherein the method further comprises forming a programming line electrically connected to the second gate. 
     
     
         4 . The method of  claim 1 , wherein a material of the charge trapping layer comprises silicon nitride. 
     
     
         5 . The method of  claim 1 , wherein a material of the top dielectric layer and the tunneling dielectric layer comprises silicon nitride. 
     
     
         6 . The method of  claim 1 , wherein a material of the first gate and the second gate comprises doped polysilicon.