SiC Film for Semiconductor Processing

Abstract

A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hard mask layers in interconnects of integrated circuits.

1 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming a transistor in the substrate;   forming a first electrically insulating layer over the transistor;   forming a second electrically insulating layer over the first electrically insulating layer; and   forming a first layer of a silicon carbide containing film over the second electrically insulating layer, said silicon carbide containing film being formed by a process comprising the steps of:
 positioning the substrate in a plasma reactor; 
 flowing 100 to 2000 sccm (standard cubic centimeters per minute) of hydrogen gas into said plasma reactor; 
 generating a plasma comprising the hydrogen gas in the plasma reactor. 
   
     
     
         2 . The method of  claim 1 , further comprising the steps of:
 forming a first layer of photoresist over said first layer of said silicon carbide containing film;   patterning the first layer of photoresist to define a first set of via regions;   etching said first layer of said silicon carbide containing film in the first set of via regions; and   etching said second electrically insulating layer in the first set of via regions.   
     
     
         3 . The method of  claim 2 , further comprising the steps of
 forming a third electrically insulating layer over said transistor;   forming a second layer of said silicon carbide containing film over the third electrically insulating layer;   forming a second layer of photoresist over the second layer of said silicon carbide containing film;   patterning the second layer of photoresist to define a first set of metal interconnect trench regions;   etching the second layer of said silicon carbide containing film in the first set of metal interconnect trench regions; and   etching the third electrically insulating layer in the first set of metal interconnect trench regions.   
     
     
         4 . The method of  claim 3 , further comprising the steps of:
 forming a third layer of said silicon carbide containing film over said transistor;   forming a fourth electrically insulating layer over the third layer of said silicon carbide containing film;   forming a third layer of photoresist over the fourth electrically insulating layer;   patterning the third layer of photoresist to define a second set of via regions; and   etching the fourth electrically insulating layer in the second set of via regions, wherein the third layer of said silicon carbide containing film is exposed in the second set of via regions.   
     
     
         5 . The method of  claim 4 , further comprising the steps of:
 forming a fifth electrically insulating layer over said transistor;   forming a fourth layer of said silicon carbide containing film over the fifth electrically insulating layer;   forming a sixth electrically insulating layer over the fourth layer of said silicon carbide containing film;   forming a fourth layer of photoresist over the sixth electrically insulating layer;   patterning the fourth layer of photoresist to define a second set of metal interconnect trench regions; and   etching the sixth electrically insulating layer in the second set of metal interconnect trench regions, wherein the fourth layer of said silicon carbide containing film is exposed in the second set of metal interconnect trench regions.   
     
     
         6 . The method of  claim 5 , further comprising the steps of:
 forming a seventh electrically insulating layer over said transistor;   forming a fifth layer of said silicon carbide containing film over the seventh electrically insulating layer;   etching the fifth layer of said silicon carbide containing film in a third set of metal interconnect trench regions;   etching the seventh electrically insulating layer in the third set of metal interconnect trench regions;   depositing liner metal and copper metal over the fifth layer of said silicon carbide containing film and in the third set of metal interconnect trench regions; and   selectively removing the liner metal and copper metal from a top surface of the fifth layer of said silicon carbide containing film.   
     
     
         7 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming a transistor in the substrate;   forming a first electrically insulating layer over the transistor;   forming a first layer of a silicon carbide containing film over the first electrically insulating layer, said silicon carbide containing film being formed by a process comprising the steps of:   positioning the substrate in a plasma reactor;   flowing 100 to 2000 sccm (standard cubic centimeters per minute) of hydrogen gas into said plasma reactor;   generating a plasma comprising the hydrogen gas in the plasma reactor;   forming a first layer of photoresist over the first layer of said silicon carbide containing film;   patterning the first layer of photoresist to define a first set of contact regions;   etching the first layer of said silicon carbide containing film in the first set of contact regions;   etching the first electrically insulating layer in the first set of contact regions;   depositing contact metal over the first layer of said silicon carbide containing film and in the first set of contact regions; and   selectively removing the contact metal from a top surface of the first layer of said silicon carbide containing film.   
     
     
         8 . The method of  claim 7 , further comprising the steps of:
 forming a second electrically insulating layer over the said transistor;   forming a second layer of said silicon carbide containing film over the second electrically insulating layer,   forming a second layer of photoresist over the second layer of said silicon carbide containing film;   patterning the second layer of photoresist to define a first set of via regions;   etching the second layer of said silicon carbide containing film in the first set of via regions; and   etching the second electrically insulating layer in the first set of via regions.   
     
     
         9 . The method of  claim 8 , further comprising the steps of:
 forming a third electrically insulating layer over said transistor;   forming a third layer of said silicon carbide containing film over the third electrically insulating layer;   forming a third layer of photoresist over the third layer of said silicon carbide containing film;   patterning the third layer of photoresist to define a first set of metal interconnect trench regions;   etching the third layer of said silicon carbide containing film in the first set of metal interconnect trench regions; and   etching the third electrically insulating layer in the first set of metal interconnect trench regions.   
     
     
         10 . The method of  claim 9 , further comprising the steps of:
 forming a fourth layer of said silicon carbide containing film over said transistor;   forming a fourth electrically insulating layer over the fourth layer of said silicon carbide containing film;   forming a fourth layer of photoresist over the fourth electrically insulating layer;   patterning the fourth layer of photoresist to define a second set of via regions; and   etching the fourth electrically insulating layer in the second set of via regions, wherein the fourth layer of said silicon carbide containing film is exposed in the second set of via regions.   
     
     
         11 . The method of  claim 10 , further comprising the steps of:
 forming a fifth electrically insulating layer over said transistor;   forming a fifth layer of said silicon carbide containing film over the fifth electrically insulating layer;   etching the fifth layer of said silicon carbide containing film in a second set of metal interconnect trench regions;   etching the fifth electrically insulating layer in the second set of metal interconnect trench regions;   depositing liner metal and copper metal over the fifth layer of said silicon carbide containing film and in the second set of metal interconnect trench regions; and   selectively removing the liner metal and copper metal from a top surface of the fifth layer of said silicon carbide containing film.   
     
     
         12 . The method of  claim 11 , further comprising the steps of:
 forming a sixth electrically insulating layer over said transistor;   forming a sixth layer of said silicon carbide containing film over the sixth electrically insulating layer;   forming a seventh electrically insulating layer over the sixth layer of said silicon carbide containing film;   forming a sixth layer of photoresist over the seventh electrically insulating layer;   patterning the sixth layer of photoresist to define a third set of metal interconnect trench regions; and   etching the seventh electrically insulating layer in the third set of metal interconnect trench regions, wherein the sixth layer of said silicon carbide containing film is exposed in the third set of metal interconnect trench regions.   
     
     
         13 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming a transistor in the substrate;   forming a first electrically insulating layer over the transistor;   forming a first layer of a silicon carbide containing film over the first electrically insulating layer, said silicon carbide containing film being formed by a process comprising the steps of:   positioning the substrate in a plasma reactor;   flowing 100 to 2000 sccm (standard cubic centimeters per minute) of hydrogen gas into said plasma reactor;   generating a plasma comprising the hydrogen gas in the plasma reactor;   forming a first layer of photoresist over the first layer of said silicon carbide containing film;   patterning the first layer of photoresist to define a first set of contact regions;   etching the first layer of said silicon carbide containing film in the first set of contact regions;   etching the first electrically insulating layer in the first set of contact regions;   
     
     
         14 . The method of  claim 13 , further comprising the steps of:
 forming a second electrically insulating layer over the said transistor;   forming a second layer of said silicon carbide containing film over the second electrically insulating layer,   forming a second layer of photoresist over the second layer of said silicon carbide containing film;   patterning the second layer of photoresist to define a first set of via regions;   etching the second layer of said silicon carbide containing film in the first set of via regions; and   etching the second electrically insulating layer in the first set of via regions.   
     
     
         15 . The method of  claim 14 , further comprising the steps of:
 forming a third electrically insulating layer over said transistor;   forming a third layer of said silicon carbide containing film over the third electrically insulating layer;   forming a third layer of photoresist over the third layer of said silicon carbide containing film;   patterning the third layer of photoresist to define a first set of metal interconnect trench regions;   etching the third layer of said silicon carbide containing film in the first set of metal interconnect trench regions; and   etching the third electrically insulating layer in the first set of metal interconnect trench regions.   
     
     
         16 . The method of  claim 15 , further comprising the steps of:
 forming a fourth layer of said silicon carbide containing film over said transistor;   forming a fourth electrically insulating layer over the fourth layer of said silicon carbide containing film;   forming a fourth layer of photoresist over the fourth electrically insulating layer;   patterning the fourth layer of photoresist to define a second set of via regions; and   etching the fourth electrically insulating layer in the second set of via regions, wherein the fourth layer of said silicon carbide containing film is exposed in the second set of via regions.   
     
     
         17 . The method of  claim 16 , further comprising the steps of:
 forming a fifth electrically insulating layer over said transistor;   forming a fifth layer of said silicon carbide containing film over the fifth electrically insulating layer;   etching the fifth layer of said silicon carbide containing film in a second set of metal interconnect trench regions;   etching the fifth electrically insulating layer in the second set of metal interconnect trench regions;   depositing liner metal and copper metal over the fifth layer of said silicon carbide containing film and in the second set of metal interconnect trench regions; and   selectively removing the liner metal and copper metal from a top surface of the fifth layer of said silicon carbide containing film.   
     
     
         18 . The method of  claim 17 , further comprising the steps of:
 forming a sixth electrically insulating layer over said transistor;   forming a sixth layer of said silicon carbide containing film over the sixth electrically insulating layer;   forming a seventh electrically insulating layer over the sixth layer of said silicon carbide containing film;   forming a sixth layer of photoresist over the seventh electrically insulating layer;   patterning the sixth layer of photoresist to define a third set of metal interconnect trench regions; and   etching the seventh electrically insulating layer in the third set of metal interconnect trench regions, wherein the sixth layer of said silicon carbide containing film is exposed in the third set of metal interconnect trench regions.   
     
     
         19 . The method of  claim 1  or  claim 7  or  claim 13 , wherein said process for forming said silicon carbide containing film further comprises the steps of:
 flowing tri-methyl silane gas into said plasma reactor; and   flowing helium gas into said plasma reactor.