Semiconductor device and method of manufacturing the same

Abstract

There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

1 . A semiconductor device comprising:
 a semiconductor substrate having a first region and a second region in a periphery of the first region;   a first MISFET provided on a main surface of the semiconductor substrate in the first region; and   a second MISFET having a breakdown voltage higher than that of the first MISFET provided on the main surface of the semiconductor substrate in the second region, wherein the first MISFET comprises:   a semiconductor layer provided on an insulating layer that is buried in the semiconductor substrate;   a first gate electrode provided on the semiconductor layer interposing a first gate insulator;   a first elevated layer provided at both sidewall sides of the first gate electrode so as to have a height from the semiconductor layer higher than that of the first gate electrode on the semiconductor layer and configuring a first source and drain of the first MISFET; and   a first semiconductor region configuring the first source and drain together with the first elevated layer and provided on the semiconductor substrate and below the first elevated layer, wherein   the second MISFET comprises:   a second gate electrode provided on the semiconductor substrate interposing a second gate insulator thicker than the first gate insulator;   a second elevated layer provided on the semiconductor substrate at both sidewall sides of the second gate electrode and configuring a second source and drain of the second MISFET; and   a second semiconductor region configuring the second source and drain together with the second elevated layer on the semiconductor substrate and below the second elevated layer, and wherein   a thickness of the first elevated layer is larger than that of the second elevated layer;   whole of the first gate electrode and the second gate electrode are silicided; and   part of the first source and drain and the second source and drain are silicided.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein a thickness of the insulating layer is smaller than or equal to 20 nm and a thickness of the semiconductor layer is smaller than or equal to 20 nm. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein an upper part or whole of the first elevated layer is silicided among the first elevated layer and the first semiconductor region configuring the first source and drain, and wherein
 whole of the second elevated layer and an upper part of the second semiconductor region are silicided among the second elevated layer and the second semiconductor region configuring the second source and drain.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 the first elevated layer is provided to be distanced from the first gate electrode side such that the highest layer is more distanced than the lowermost layer of a plurality of layers in proportion.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 the first gate electrode and second gate electrode are silicided films of Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa or Ru.   
     
     
         6 . A method of manufacturing a semiconductor device comprising the steps of:
 (a) preparing a substrate that includes: a semiconductor substrate having a first region in which a first MISFET is formed and a second region in a periphery of the first region in which a second MISFET is formed; and a semiconductor layer on an insulating layer buried in the semiconductor substrate;   (b) removing the semiconductor layer and the insulating layer in the second region to expose the semiconductor substrate in the second region;   (c) forming a first gate electrode on the semiconductor layer in the first region interposing a first gate insulator;   (d) forming a second gate electrode interposing a second gate insulator that is thicker than the first gate insulator on the semiconductor substrate in the second region;   (e) forming a first extension layer having an impurity concentration higher than that of the semiconductor layer at both sidewall sides of the second gate electrode on the semiconductor substrate;   (f) depositing a first insulating film on the whole of a surface of the substrate and performing anisotropic etching to leave the first insulating films on both sidewalls of the first gate electrode and on both sidewalls of the second gate electrode after the step (e);   (g) forming a first elevated layer at both sidewall sides of the first gate electrode on the semiconductor layer by a selective epitaxial growth with taking the semiconductor layer as a base after the step (f);   (h) forming a second elevated layer at both sidewall sides of the second gate electrode on the semiconductor substrate by a selective epitaxial growth with taking the first extension layer as a base after the step (f);   (i) forming a first diffusion layer configuring a first source and drain of the first MISFET by implanting a first impurity into the first elevated layer and the semiconductor layer below the first elevated layer and diffusing the first impurity after the steps (g) and (h);   (j) forming a second diffusion layer configuring a second source and drain of the second MISFET by implanting a second impurity into the second elevated layer and the semiconductor substrate below the second elevated layer and diffusing the second impurity after the steps (g) and (h);   (k) removing the first insulating film after the steps (i) and (j); and   (l) forming a second extension layer at both sidewall sides of the first gate electrode on the semiconductor layer.   
     
     
         7 . The method of manufacturing the semiconductor device according to  claim 6 , further comprising the steps of:
 (m) depositing a second insulating film on the whole surface of the substrate and performing the anisotropic etching to leave the second insulating film on both sidewalls of the second gate electrode, the second gate electrode, both sidewalls of the first elevated layer and the second elevated layer after the step (l); and   (n) depositing a metal film on the whole surface of the substrate and giving thermal processing to silicide the whole of the first gate electrode, the whole of the second gate electrode, part of the first source and drain, and part of the second source and drain after the step (m).   
     
     
         8 . The method of manufacturing the semiconductor device according to  claim 6 , wherein
 the step (a) prepares the substrate to have the thickness of the insulating layer being smaller than or equal to 20 nm and the thickness of the semiconductor layer is smaller than or equal to 20 nm.   
     
     
         9 . The method of manufacturing the semiconductor device according to  claim 7 , wherein
 the step (n) silicides an upper part or the whole of the first elevated layer configuring the first source and drain, and silicides the whole of the second elevated layer configuring the second source and drain and the semiconductor substrate below the second elevated layer.   
     
     
         10 . The method of manufacturing the semiconductor device according to  claim 7 , wherein
 the step (n) deposits the metal films by Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa or Ru.   
     
     
         11 . A method of manufacturing a semiconductor device comprising the steps of:
 (a) preparing a substrate that includes: a semiconductor substrate having a first region in which a first MISFET is formed and a second region in a periphery of the first region in which a second MISFET is formed; and a semiconductor layer on an insulating layer buried in the semiconductor substrate;   (b) removing the semiconductor layer and the insulating layer in the second region to expose the semiconductor substrate in the second region;   (c) forming a first gate electrode on the semiconductor layer in the first region interposing a first gate insulator;   (d) forming a second gate electrode interposing a second gate insulator that is thicker than the first gate insulator on the semiconductor substrate in the second region;   (e) forming a first extension layer having an impurity concentration higher than that of the semiconductor layer at both sidewall sides of the second gate electrode on the semiconductor substrate;   (f) depositing a first insulating film on the whole of a surface of the substrate and performing anisotropic etching to leave the first insulating films on both sidewalls of the first gate electrode and on both sidewalls of the second gate electrode after the step (e);   (g) forming a first lowermost layer configuring a first elevated layer at both sidewall sides of the first gate electrode on the semiconductor layer by a selective epitaxial growth with taking the semiconductor layer as a base after the step (f);   (h) forming a second lowermost layer configuring a second elevated layer at both sidewall sides of the second gate electrode on the semiconductor substrate by a selective epitaxial growth with taking the first extension layer as a base after the step (f);   (i) depositing the second insulating film on the whole surface of the substrate and performing the anisotropic etching to leave the second insulating film on both sidewalls of the first gate electrode and on both sidewalls of the second gate electrode after the steps (g) and (h);   (j) forming a first upper layer configuring the first elevated layer on both sidewalls of the first gate electrode of the first lowermost layer by a selective epitaxial growth with taking the first lowermost layer as a base after the step (i);   (k) forming a second upper layer configuring the second elevated layer on both sidewalls of the second gate electrode of the second lowermost layer by the selective epitaxial growth with the second lowermost layer taken as a base after the step (i);   (l) forming a first diffusion layer configuring a first source and drain of the first MISFET by implanting a first impurity into the first elevated layer and the semiconductor layer below the first elevated layer and diffusing the first impurity after the steps (j) and (k);   (m) forming a second diffusion layer configuring a second source and drain of the second MISFET by implanting a second impurity into the second elevated layer and the semiconductor substrate below the second elevated layer and diffusing the second impurity after the steps (j) and (k);   (n) removing the second insulating film and the first insulating film after the steps (l) and (m); and   (o) forming a second extension layer on the semiconductor layer at both sidewalls of the first gate electrode.   
     
     
         12 . The method of manufacturing the semiconductor device according to  claim 11 , further comprising the steps of:
 (p) depositing a third insulating film on the whole surface of the substrate and performing the anisotropic etching to leave the third insulating film on both sidewalls of the second gate electrode, the second gate electrode, both sidewalls of the first elevated layer and the second elevated layer after the step (o); and   (q) depositing a metal film on the whole surface of the substrate and giving thermal processing to silicide the whole of the first gate electrode, the whole of the second gate electrode, part of the first source and drain, and part of the second source and drain after the step (p).   
     
     
         13 . The method of manufacturing the semiconductor device according to  claim 11 , wherein
 the step (a) prepares the substrate to have the thickness of the insulating layer being smaller than or equal to 20 nm and the thickness of the semiconductor layer is smaller than or equal to 20 nm.   
     
     
         14 . The method of manufacturing the semiconductor device according to  claim 12 , wherein
 the step (q) silicides an upper part or the whole of the first elevated layer configuring the first source and drain, and silicides the whole of the second elevated layer configuring the second source and drain and the semiconductor substrate below the second elevated layer.   
     
     
         15 . The method of manufacturing the semiconductor device according to  claim 12 , wherein
 the step (q) deposits the metal films by Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa or Ru.