Phase change memory device with improved performance that minimizes cell degradation

Abstract

A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data. The sense amplifier is configured to compare a reference voltage with a sensing voltage received from the cell array. The write driving unit is configured to supply a driving voltage corresponding to write data to the cell array. The reference level selecting unit is configured to select a read reference voltage in a read mode so as to output the reference voltage, and to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage.

1 . A phase change memory device comprising:
 a cell array including a phase change resistor configured to read/write data;   a sense amplifier configured to compare a reference voltage with a sensing voltage received from the cell array;   a write driving unit configured to supply a driving voltage corresponding to write data to the cell array; and   a reference level selecting unit configured to select a read reference voltage in a read mode so as to output the reference voltage, to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage.   
     
     
         2 . The phase change memory device according to  claim 1 , wherein the reference level selecting unit selects a set reference voltage when the input data is a set data and selects a reset reference voltage when the input data is a reset data. 
     
     
         3 . The phase change memory device according to  claim 1 , wherein the reference level selecting unit includes:
 a read reference switch configured to output the read reference voltage with the reference voltage in response to a reference enable signal;   a set reference switching unit configured to combine the input data with the reference enable signal so as to output a set reference voltage with the reference voltage; and   a reset reference switching unit configured to combine the input data with the reference enable signal so as to output a reset reference voltage with the reference voltage.   
     
     
         4 . The phase change memory device according to  claim 3 , wherein the set reference switching unit includes:
 a set reference enable unit configured to output an activating signal when the reference enable signal is inactivated and the input data is the set data; and   a set reference switch configured to output a set reference voltage with the reference voltage in response to an output signal of the set reference enable unit.   
     
     
         5 . The phase change memory device according to  claim 3 , wherein the reset reference switching unit includes:
 a reset reference enable unit configured to output an activating signal when the reference enable signal is inactivated and the input data is the reset data; and   a reset reference switch configured to output a reset reference voltage with the reference voltage in response to an output signal of the reset reference enable unit.   
     
     
         6 . The phase change memory device according to  claim 1 , wherein the sense amplifier includes:
 a sensing current voltage converting unit configured to convert a sensing current received from the cell array into the sensing voltage;   an amplifier configured to compare and amplify the sensing voltage and the reference voltage; and   a latch unit configured to latch an output signal of the amplifier.   
     
     
         7 . The phase change memory device according to  claim 6 , wherein the sensing current voltage converting unit includes:
 a precharge unit configured to precharge the sensing voltage to have a high voltage in response to a first precharge signal;   a sensing current adjusting unit configured to adjust a level of the sensing voltage in response to an adjusting signal;   a clamp voltage adjusting unit configured to adjust a clamp voltage of a global bit line in response to a clamp signal; and   a clamp voltage precharge unit configured to precharge the global bit line in response to the clamp signal.   
     
     
         8 . The phase change memory device according to  claim 1 , further comprising:
 an output adjusting unit configured to control an output signal of the sense amplifier so as to output the output signal to a global input/output line;   a data input latch unit configured to latch data of the global input/output line so as to output the input data; and   a comparing unit configured to compare the input data with output data of the sense amplifier so as to output a driving enable signal for controlling the write driving unit.   
     
     
         9 . The phase change memory device according to  claim 8 , further comprising a data input/output buffer unit configured to buffer input/output data of the global input/output line. 
     
     
         10 . The phase change memory device according to  claim 8 , wherein the comparing unit activates the driving enable signal when a level of output data of the sense amplifier is different from that of the input data. 
     
     
         11 . The phase change memory device according to  claim 1 , further comprising:
 a main reference voltage supply unit configured to generate the reference voltage having a different level from the read reference voltage and the reference voltage; and   a reference mode adjusting unit configured to select the read reference voltage or the reference voltage in a read mode so as to generate a reference enable signal.   
     
     
         12 . The phase change memory device according to  claim 1 , further comprising:
 a pull-down unit configured to pull down a global bit line connected to the cell array in a precharge mode; and   a global column switching unit configured to selectively control connection of the sense amplifier with the global bit line in response to a global column switching signal.   
     
     
         13 . A phase change memory device comprising:
 a cell array including a phase change resistor configured to read/write data;   a plurality of sense amplifiers configured to compare multi-voltage levels of a reference voltage signal with a multi-voltage levels of a sensing voltage signal received from the cell array;   a plurality of write driving units configured to supply multi-voltage levels of a driving voltage signal corresponding to write data to the cell array; and   a reference level selecting unit configured to select a multi-voltage levels of a read reference voltage signal in a read mode so as to output the reference voltage signal and to select one voltage level of the reference voltage signal corresponding to input data in a write verifying mode so as to output the one voltage level of the reference voltage signal.   
     
     
         14 . The phase change memory device according to  claim 13 , wherein the number of the sense amplifiers and the write driving units is 2 N −1 when N-bit data is sensed (N is a natural number). 
     
     
         15 . The phase change memory device according to  claim 13 , wherein each of the sense amplifiers receives a first voltage level of a read reference voltage signal in the read mode and a second voltage level of a first reference voltage signal having and a third voltage level of a second reference voltage signal in the write verifying mode. 
     
     
         16 . The phase change memory device according to  claim 13 , wherein the reference level selecting unit includes:
 a read reference switch configured to output the read reference voltage signal with the reference voltage signal in response to a reference enable signal;   a first reference switching unit configured to combine the input data with the reference enable signal so as to output a first reference voltage signal with the reference voltage signal; and   a second reference switching unit configured to combine the input data logically with the reference enable signal so as to output a second reference voltage signal with the reference voltage signal.   
     
     
         17 . The phase change memory device according to  claim 13 , wherein the sense amplifier includes:
 a sensing current voltage converting unit configured to convert a multi-level sensing current received from the cell array into the sensing voltage signal;   an amplifier configured to compare and amplify the reference voltage signal with the sensing voltage signal; and   a latch unit configured to latch an output signal of the amplifier.   
     
     
         18 . The phase change memory device according to  claim 17 , wherein the sensing current voltage converting unit includes:
 a precharge unit configured to precharge the sensing voltage signal to a high level in response to a first precharge signal;   a sensing current adjusting unit configured to adjust a voltage level of the sensing voltage signal in response to an adjusting signal;   a clamp voltage adjusting unit configured to adjust a clamp voltage signal of a global bit line in response to a clamp signal; and   a clamp voltage precharge unit configured to precharge the global bit line in response to the clamp signal.   
     
     
         19 . The phase change memory device according to  claim 13 , further comprising:
 an output adjusting unit configured to control an output signal of the sense amplifier so as to output the output signal to a global input/output line;   a data input latch unit configured to latch data of the global input/output line so as to output the input data; and   a comparing unit configured to compare the input data with output data of the sense amplifier so as to output a driving enable signal for controlling the write driving unit.   
     
     
         20 . The phase change memory device according to  claim 19 , further comprising a data input/output buffer unit configured to buffer input/output data of the global input/output line. 
     
     
         21 . The phase change memory device according to  claim 19 , wherein the comparing unit activates the driving enable signal when a level of output data of the sense amplifier is different from that of the input data. 
     
     
         22 . The phase change memory device according to  claim 13 , further comprising:
 a main reference voltage supply unit configured to generate the reference voltage signal having a different voltage level from those of the read reference voltage signal and the read reference voltage signal; and   a reference mode adjusting unit configured to generate a reference enable signal for selecting the read reference voltage signal or the reference voltage signal in the read mode.