Phase Change Memory with Diodes Embedded in Substrate

Abstract

An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

1 . An integrated circuit structure comprising:
 a semiconductor substrate;   a diode comprising:
 a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and 
 a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type; and 
   a phase change element over and electrically connected to the diode.   
   
   
       2 . The integrated circuit structure of  claim 1 , wherein the phase change material comprises a chalcogenide material. 
   
   
       3 . The integrated circuit structure of  claim 1  further comprising:
 a plurality of heavily doped semiconductor strips; and   a plurality of diodes arranged as an array having a plurality of rows and columns, wherein each of the rows has one of the heavily doped semiconductor strips underlying, and adjoining, the row of the plurality of diodes.   
   
   
       4 . The integrated circuit structure of  claim 3  further comprising a plurality of metal lines over the semiconductor substrate and extending in a column direction, wherein each of the plurality of diodes is coupled between one of the plurality of heavily doped semiconductor strips and one of the plurality of metal lines. 
   
   
       5 . The integrated circuit structure of  claim 4  further comprising a plurality of silicide regions, wherein a first portion of the silicide regions is on the plurality of diodes, and wherein a second portion of the silicide regions are on pickup regions of the heavily doped semiconductor strips. 
   
   
       6 . The integrated circuit structure of  claim 4 , wherein the plurality of rows of the array is separated from each other by shallow trench isolation (STI) regions, and wherein the plurality of columns of the array is separated from each other by shallow STI regions having a smaller depth than the STI regions. 
   
   
       7 . An integrated circuit structure comprising:
 a semiconductor substrate;   a diode array comprising a plurality of diodes embedded in the semiconductor substrate and arranged as rows and columns, each of the plurality of diodes comprising:
 a first doped semiconductor region of a first conductivity type; 
 a second doped semiconductor region over, and adjoining, the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type; and 
   a plurality of heavily doped semiconductor strips of the first conductivity type, each underlying and connected to a row of the diodes and adjoining the first doped semiconductor region of the row of the diodes.   
   
   
       8 . The integrated circuit structure of  claim 1  further comprising a plurality of silicide regions substantially level with a top surface of the semiconductor substrate, wherein each of the plurality of silicide regions is overlying and adjoining the second doped semiconductor region of one of the plurality of diodes. 
   
   
       9 . The integrated circuit structure of  claim 8  further comprising:
 a plurality of heavily doped pickup regions in the semiconductor substrate, each adjoining one of the plurality of heavily doped semiconductor strips; and   a plurality of pickup silicide regions substantially level with the top surface of the semiconductor substrate, wherein each of the plurality of pickup silicide regions is overlying and adjoining one of the plurality of heavily doped pickup regions.   
   
   
       10 . The integrated circuit structure of  claim 1  further comprising a plurality of phase change elements, each electrically connected to one of the plurality of diodes. 
   
   
       11 . The integrated circuit structure of  claim 1 , wherein the first conductivity type is n-type, and the second conductivity type is p-type. 
   
   
       12 . An integrated circuit structure comprising:
 a semiconductor substrate;   a plurality of word-lines embedded in the semiconductor substrate;   a diode array comprising a plurality of diodes arranged as rows and columns, wherein the plurality of diodes are embedded in the semiconductor substrate and overlying the plurality of word-lines;   a plurality of insulating regions in the semiconductor substrate and separating the rows of the plurality of the diodes from each other;   a plurality of shallow insulating regions in the semiconductor substrate and separating the columns of the plurality of the diodes from each other, wherein the plurality of shallow insulating regions has a thickness less than a thickness of the plurality of insulating regions; and   a plurality of phase change elements, each overlying, and electrically connected to, one of the plurality of diodes.   
   
   
       13 . The integrated circuit structure of  claim 12 , wherein the plurality of word-lines are underlying the plurality of diodes. 
   
   
       14 . The integrated circuit structure of  claim 12  further comprising a plurality of bit-lines in a metallization layer over the semiconductor substrate, wherein each of the plurality of bit-lines is electrically connected to one of the plurality of phase change elements. 
   
   
       15 . The integrated circuit structure of  claim 12  further comprising:
 a plurality of heavily doped pickup regions in the semiconductor substrate, each electrically connected to one of the plurality of word-lines;   a plurality of pickup silicide regions, wherein each of the plurality of pickup silicide regions is overlying and adjoining one of the plurality of heavily doped pickup regions; and   a MOS device at a top surface of the semiconductor substrate, wherein the MOS device comprises at least a silicide region formed of a same material as the plurality of pickup silicide regions.