Dual depth trench termination method for improving cu-based interconnect integrity

Abstract

A trench is formed in a low K dielectric ( 100 ) over a plurality of vias ( 120 ) also formed in the low K dielectric layer ( 100 ). The vias are separated by a distance of less than X V and the edge of the trench is greater than X TO from the edge α of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper ( 150, 160 ) to form the interconnect line.

1 - 4 . (canceled) 
   
   
       5 . An integrated circuit copper layer, comprising:
 a low K dielectric layer over a semiconductor;   a plurality of vias in a first region of said low K dielectric layer;   a trench with a first edge in said low K dielectric layer over said plurality of vias wherein said trench extends a minimum length X TO  beyond the edge a of a via closest to the first edge of said trench; and   a copper layer with a first edge in said trench and said plurality of vias wherein said first edge of said copper layer coincides with said first edge of said trench and extends a minimum length X TO  beyond the edge a of said via closest to the first edge of said trench.   
   
   
       6 . The integrated circuit layer of  claim 5  wherein said copper layer comprises a first thickness t 1  in said first region and a second thickness t 2  at said first edge wherein t 1  is greater than t 2 . 
   
   
       7 . The integrated circuit copper layer of  claim 5  wherein said minimum length X TO  is 0.2 um. 
   
   
       8 . The integrated circuit copper layer of  claim 7  wherein 5 said plurality of vias are separated by a distance less than 1.0 um. 
   
   
       9 . (canceled)