Semiconductor device

Abstract

A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line.

1 . A semiconductor device comprising:
 a first latch circuit;   a second latch circuit coupled to the first latch circuit, and for receiving an output of the first latch circuit;   a first switching element provided between the first latch circuit and the second latch circuit;   a feedback line for feeding data held by the second latch circuit to the first latch circuit; and   a second switching element provided on the feedback line.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 an input line coupled to the first latch circuit; and   a third switching element provided on the input line.   
     
     
         3 . The semiconductor device according to  claim 1 , further comprising a clock generating circuit for controlling operations of the first switching element, the second switching element, and the third switching element. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein the second switching element is in an ON state during at least a part of a period during which the third switching element is in an OFF state. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the second switching element is in an ON state during at least a part of a period during which the first switching element is in an ON state. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the first switching element and the second switching element perform ON-OFF operations in synchronization with each other. 
     
     
         7 . The semiconductor device according to  claim 2 , wherein the third switching element performs an ON-OFF operation in reverse of an ON-OFF operation of the second switching element. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the first latch circuit and the second latch circuit each have a loop circuit including a plurality of inverters. 
     
     
         9 . A semiconductor device comprising:
 a first latch circuit;   a second latch circuit;   a first transmission line for transmitting an output of the first latch circuit to the second latch circuit;   a second transmission line for transmitting an output of the second latch circuit to the first latch circuit;   a first switching element provided on the first transmission line; and   a second switching element provided on the second transmission line.   
     
     
         10 . The semiconductor device according to  claim 9 , further comprising:
 an input line coupled to the first latch circuit; and   a third switching element provided on the input line.   
     
     
         11 . The semiconductor device according to  claim 1 , further comprising a clock generating circuit for controlling operations of the first switching element, the second switching element, and the third switching element. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein the second switching element is in an ON state during at least a part of a period during which the third switching element is in an OFF state. 
     
     
         13 . The semiconductor device according to  claim 9 , wherein the second switching element is in an ON state during at least a part of a period during which the first switching element is in an ON state. 
     
     
         14 . The semiconductor device according to  claim 9 , wherein the first switching element and the second switching element perform ON-OFF operations in synchronization with each other. 
     
     
         15 . The semiconductor device according to  claim 10 , wherein the third switching element performs an ON-OFF operation in reverse of an ON-OFF operation of the second switching element. 
     
     
         16 . The semiconductor device according to  claim 9 , wherein the first latch circuit and the second latch circuit each have a loop circuit including a plurality of inverters.