Data Holding Circuit

Abstract

A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.

1 . A data holding circuit comprising:
 a first input terminal through which data is inputted;   at least one delay element for delaying the data inputted through said first input terminal; and   a first element for holding data wherein, when the data inputted through said first input terminal and the data delayed by said delay element are equal to each other, the first element holds data corresponding to the data inputted through said first input terminal and, when the data inputted through said first input terminal and the data delayed by said delay element are different from each other, the first element continues to hold data presently held by the first element.   
     
     
         2 . The data holding circuit according to  claim 1 , wherein said first element includes:
 a comparison circuit wherein, when the data inputted through said first input terminal and the data delayed by said delay element are equal to each other, the comparison circuit outputs data corresponding to the data inputted through said first input terminal and wherein, when the data inputted through said first input terminal and the data delayed by said delay element are different from each other, the comparison circuit brings the output into a high impedance state; and   a first data holding element for holding the output data of said comparison circuit.   
     
     
         3 . The data holding circuit according to  claim 2 , further comprising:
 a second data holding element for holding data outputted from said first data holding element; and   a clock switch connected between said first and said second data holding elements for performing an ON/OFF operation in response to a clock signal.   
     
     
         4 . The data holding circuit according to  claim 2 , wherein
 in said comparison circuit, the output goes into a high impedance state in response to a clock signal.   
     
     
         5 . The data holding circuit according to  claim 1 , further comprising:
 a second input terminal through which data is inputted;   a first switch connected between said first input terminal and said delay element; and   a second switch connected between said second input terminal and said delay element, wherein   when said first switch enters an ON state, said second switch enters an OFF state, said first element receives the data inputted through said first input terminal and the data is inputted through said first input terminal via said delay element, and wherein   when said second switch enters an ON state, said first switch enters an OFF state, said first element receives the data inputted through said second input terminal and the data is inputted through said second input terminal via said delay element.   
     
     
         6 . A data holding circuit comprising:
 a first input terminal through which data is inputted;   a comparison circuit having at least three input terminals for outputting data corresponding to a large number of data pieces in data provided on the at least three input terminals;   at least three switches connected between said first input terminal and the at least three input terminals of said comparison circuit, the at least three switches going from an ON state to an OFF state at mutually different timings; and   a first data holding element for holding data outputted from said comparison circuit.   
     
     
         7 . The data holding circuit according to  claim 6 , wherein
 the at least three input terminals of said comparison circuit go into a floating state when said at least three switches enter an OFF state, respectively.   
     
     
         8 . The data holding circuit according to  claim 6 , further comprising:
 a second data holding element for holding data outputted from said first data holding element; and   a clock switch connected between said first and said second data holding elements and for performing an ON/OFF operation in response to a clock signal.   
     
     
         9 . The data holding circuit according to  claim 8 , wherein
 said clock switch performs an ON/OFF operation opposite to the operation of one switch of said at least three switches.   
     
     
         10 . The data holding circuit according to  claim 9 , wherein
 said clock switch performs an ON/OFF operation opposite to the operation of one switch going from the ON state to the OFF state at the latest timing among said three or more switches.