Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates

Abstract

In a test and debug system in which a plurality of modules under test have different operational rates, the system clock and the return clock signals from the modules lose synchronism. An error signal is produced when the clock signal makes a transition to a logic state that is the same logic state of the return clock signal of all of the modules. Apparatus is provided for generating logic signals when all of the return clock signals are in the same logic state. Two logic states are possible for all the return clock signals. A current state is latched until all the return clock signals are in the other state, at which time the second logic signal state is latched. The apparatus can be reset by an external signal.

1 . In a test and debug system having a plurality of modules operating at different rates, the modules receiving a common CLK signal and each module generating an RCLK signal, the method for providing an ERROR signal comprising:
 combining the RCKL signals in a composite RCLK signal;   comparing the composite RCLK signal with the CLK signal; and   generating an ERROR signal when a transition of one signal results in the same state as the other signal.   
   
   
       2 . The method as recited in  claim 1  further comprising:
 generating a composite; RCLK signal when the RCLK signals from the modules all have the same state; and   latching the most recent composite RCLK signal.   
   
   
       3 . The method as recited in  claim 1  wherein the test and debug system uses the JTAG format. 
   
   
       4 . The method as recited in  claim 1  further comprising initializing the apparatus generating the ERROR signal with a combination of the ERROR signal and an external signal. 
   
   
       5 . An apparatus for detecting an error in the clocking of a test and debug procedure, the apparatus comprising;
 a plurality of modules processing data signals applied thereto at different rates, the modules having a clock signal applied thereto, each module generating a return clock signal;   an first adder circuit having the return clock signals applied thereto, the first adder circuit generating a first signal when all of the return clock signals have first logic state;   a second adder circuit having the return clock signals applied thereto, the second adder circuit generating a second signal when the return clock signal have second logic state;   a latching circuit for latching the most recently generated to the first and the second output signal, and   a comparison circuit responsive to the clock signal, the first signal and the second signal, the comparison circuit generating an ERROR signal when the clock signal transition to the same logic state of the first or second signal.   
   
   
       6 . The apparatus as recited in  claim 5  wherein the test and debug procedure is a JTAG procedure. 
   
   
       7 . The apparatus as recited in  claim 5  further comprising a reset circuit responsive to the ERROR signal and an external signal, the reset circuit removing the ERROR signal. 
   
   
       8 . In a test and debug system wherein a plurality of modules under test operates at different rates, an apparatus for generating a ERROR signal when a clock error is identified, the apparatus comprising:
 a first summing circuit responsive to the return clock signals from the modules, the first summing circuit generating a first logic signal when all of the return clock signals have a first preselected value;   a second summing circuit responsive to the return clock signals from the modules, the second summing circuit generating a second logic signal when all of the return clock signals have a second preselected value;   a latching circuit having the first and the second preselected value applied thereto, the latching circuit latching one logic signal until the other logic signal is generated; and   a comparison circuit, the comparison circuit comparing the output signal of the latch circuit to a system clock signal, the comparison circuit generating an ERROR signal when the output signal has predetermined relationship with the system clock signal.   
   
   
       9 . The apparatus as recited in  claim 8  wherein the test and debug system is a JTAG test and debug system. 
   
   
       10 . The apparatus as recited  claim 8  wherein the modules being tested include module in processing machines by ARM Corporation. 
   
   
       11 . The apparatus as recited in  claim 10  wherein the predetermined relationship is an identity in the logic state of the system clock and the logic state of the of RCLK. 
   
   
       12 . The apparatus as recited in  claim 8  further comprising a reset circuit, the reset circuit responsive to the ERROR signal and an external signal for removing the ERROR signal.