Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates

Abstract

In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the adder unit, the adder unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an adder unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the adder unit. it.

1 . In a test and debug system having a plurality of modules under test, a selection unit coupled to each module, the selection unit comprising:
 a first unit responsive to a system clock signal, a RCLK signal, and a SELECT signal, the first unit providing a GATE signal and a GATE_RET signal; and   a second unit responsive to the GATE and the GATE_RET signal for generating a RCLK_PE signal and a RCLK_NE signal.   
   
   
       2 . The selection unit as recited in  claim 1  wherein, in response to a SELECT signal, the RCLK_PE signal and the RCLK_NE are generated in synchronism with the RCLK signal. 
   
   
       3 . The selection unit as recited in  claim 1  wherein, in the absence of the SELECT signal, the RCLK_NE and the RCLK_PE signal is generated continuously. 
   
   
       4 . The selection unit as recited in  claim 1  wherein the test and debug system has a JTAG format. 
   
   
       5 . A method for applying a module RCKL signal to an adder unit to form a composite RCLK signal, the method comprising:
 applying a RCLk_NE signal and a RCLK_PE signal synchronized with the RCLK signal when a SELECT signal is applied; and   applying a RCLK_NE signal and a RCLK PE signal continuously when a SELECT signal is not applied.   
   
   
       6 . The method as recited in  claim 5  further comprising comparing the composite RCLK signal and the CLK signal. 
   
   
       7 . The method as recited in  claim 6  further comprising generating an ERROR signal when the CLK signal and the RCLK signal have a preselected relationship. 
   
   
       8 . In a test and debug unit system, an apparatus for generating a composite RCLK signal, the apparatus comprising:
 A plurality of modules, each module processing data in signals at different rates;   An adder unit;   a selection unit coupled to each module, the selection unit having the RCLK signal from the coupled module applied thereto, the selection unit applying RCLK_PE and RCLK_NE signals synchronized with the RCLK signal to the adder unit when a control signal is applied to the selection unit, the selection unit applying continuous RCLK_PE and RCLK_NE signals to the adder unit when the first control signal is not applied to the selection unit;   wherein the adder unit generates a composite RCLK signal for the selected modules.   
   
   
       9 . The apparatus as recited in  claim 8  further comprising a comparator, the comparator comparing the CLK signal and the composite RCLK signal, the comparator generating an ERROR signal when the CLK signal and the RCLK signal have a preselected relationship. 
   
   
       10 . The apparatus as recited in  claim 9  wherein the ERROR signal is generated when the composite RCLK signal transitions to the same logic state as the CLK signal.