Semiconductor device

Abstract

A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.

1 . A semiconductor device comprising an inverter circuit that includes:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type formed in the substrate;   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in different regions from each other in the deep-well;   a second field effect transistor of the second conductivity type formed in the first shallow well; and   a first field effect transistor of the first conductivity type and formed in the second shallow well, wherein   a first gate electrode of the first field effect transistor and a second gate electrode of the second field effect transistor are directly or indirectly connected to: the substrate; a portion having a substrate potential; the deep-well; a shallow well of the first conductivity type; a shallow well of the second conductivity type; or a predetermined portion regarding circuit operations by using a first wiring, and the first shallow well is directly or indirectly connected to the substrate or a portion having a substrate potential by using a second wiring included in a layer lower than the first wiring, and wherein   a number of connection holes formed in an insulating film just above the first wiring is less than a number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the second wiring is a wiring of a first layer. 
   
   
       4 . The semiconductor device according to  claim 1 , wherein the deep-well is not connected to the substrate. 
   
   
       5 . The semiconductor device according to  claim 1 , wherein the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected by a conductive material of a same layer configuring both the first and second gate electrodes. 
   
   
       6 . The semiconductor device according to  claim 1 , wherein the first gate electrode of the first field effect transistor is formed of a stacked film of a silicon film of the first conductivity type and a silicide layer; the second gate electrode of the second field effect transistor is formed of a stacked layer of a silicon film of the second conductivity type and a silicide layer of the same layer as the silicide layer of the first field effect transistor; and the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected to each other by the silicide layer. 
   
   
       7 . The semiconductor device according to  claim 1 , wherein the inverter circuit does not contribute to circuit operations. 
   
   
       8 . The semiconductor device according to  claim 1 , wherein charges which have flowed into the deep-well or the second shallow well are discharged to the substrate or a portion having a substrate potential via the first shallow well and the second wiring. 
   
   
       9 . A semiconductor device comprising an inverter circuit that includes:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a first shallow well of the first conductivity type and formed in a region other than the deep-well;   a second shallow well of the second conductivity type and formed in the deep-well;   a second field effect transistor of the second conductivity type and formed in the first shallow well; and   a first field effect transistor of the first conductivity type and formed in the second shallow well, wherein a first gate electrode of the first field effect transistor and a second gate electrode of the second field effect transistor are directly or indirectly connected to: the substrate; a portion having a substrate potential; the deep-well; a shallow well of the first conductivity type; a shallow well of the second conductivity type; or a predetermined portion regarding circuit operations by using a first wiring, and wherein   a number of connection holes formed in an insulating film just above the first wiring is less than a number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       10 . The semiconductor device according to  claim 9 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       11 . The semiconductor device according to  claim 9 , wherein the deep-well is not connected to the substrate. 
   
   
       12 . The semiconductor device according to  claim 9 , wherein the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected by a conductive material of a same layer configuring both the first and second gate electrodes. 
   
   
       13 . The semiconductor device according to  claim 9 , wherein the first gate electrode of the first field effect transistor is formed of a stacked film of a silicon film of the first conductivity type and a silicide layer; the second gate electrode of the second field effect transistor is formed of a stacked layer of a silicon film of the second conductivity type and a silicide layer of the same layer as the silicide layer of the first field effect transistor; and the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected to each other by the silicide layer. 
   
   
       14 . The semiconductor device according to  claim 9 , wherein the inverter circuit does not contribute to circuit operations. 
   
   
       15 . The semiconductor device according to  claim 9 , wherein charges which have flowed into the deep-well or the second shallow well are discharged to the substrate via the first shallow well. 
   
   
       16 . A semiconductor device comprising an inverter circuit that includes:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a second shallow well of the second conductivity type and formed in the deep-well;   a first shallow well of the first conductivity type and formed in a region other than the second shallow well and not connected to either of one or more portions having a substrate potential, the deep-well, or one or more shallow wells of the second conductivity type;   a second field effect transistor of the second conductivity type and formed in the first shallow well; and   a first field effect transistor of the first conductivity type and formed in the second shallow well, wherein   a first gate electrode of the first field effect transistor and a second gate electrode of the second field effect transistor are directly or indirectly connected to: the substrate; the one or more portions having a substrate potential; the deep-well; a shallow well of the first conductivity type; the one or more shallow wells of the second conductivity type; or a predetermined portion regarded by circuit operations by using a first wiring, and wherein   a number of connection holes formed in an insulating film just above the first wiring is less than a number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       17 . The semiconductor device according to  claim 16 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       18 . The semiconductor device according to  claim 16 , wherein the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected by a conductive material of a same layer configuring both the first and second gate electrodes. 
   
   
       19 . The semiconductor device according to  claim 16 , wherein the first gate electrode of the first field effect transistor is formed of a stacked film of a silicon film of the first conductivity type and a silicide layer; the second gate electrode of the second field effect transistor is formed of a stacked layer of a silicon film of the second conductivity type and a silicide layer of the same layer as the silicide layer of the first field effect transistor; and the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor are connected to each other by the silicide layer. 
   
   
       20 . The semiconductor device according to  claim 16 , wherein the inverter circuit does not contribute to circuit operations. 
   
   
       21 . The semiconductor device according to  claim 16 , wherein charges which have flowed into the deep-well or the second shallow well are discharged to the substrate via the second shallow well and the deep-well. 
   
   
       22 . A semiconductor device comprising an inverter circuit that includes:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in different regions from each other in the deep-well;   a second field effect transistor of the second conductivity type and formed in the first shallow well; and   a first field effect transistor of the first conductivity type and formed in the second shallow well, wherein   a gate electrode of the first field effect transistor and a gate electrode of the second field effect transistor are directly or indirectly connected to: the substrate; a portion having a substrate potential; or a portion having a power-supply voltage by using a first wiring, and wherein   a number of connection holes formed in an insulating film just above the first wiring is less than a number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       23 . A semiconductor device comprising:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate; and   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in the deep-well, wherein   at least one of the deep-well, the first shallow well, and the second shallow well is directly or indirectly connected to the substrate or a portion having a substrate potential by using a first wiring, and   a number of connection holes formed in an insulating film just above the first wiring is less than a number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       24 . The semiconductor device according to  claim 22 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       25 . A semiconductor device comprising:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate; and   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in different regions from each other in the deep-well, wherein   a portion in the second shallow well and the substrate or a portion in a well having a substrate potential are directly or indirectly connected to each other by a first wiring, and   the number of connection holes formed in an insulating film just above the first wiring is less than the number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       26 . A semiconductor device comprising:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a second shallow well of the second conductivity type and formed in the deep-well; and   a first shallow well of the first conductivity type and formed in a region other than the second shallow well in the deep-well, and not connected to one or more wells having a substrate potential, the deep-well, or one or more shallow wells of the second conductivity type, wherein   a portion in the first shallow well and the substrate, a portion in the one or more wells having a substrate potential, or a portion in the one or more shallow wells of the second conductivity type are directly or indirectly connected to each other by a first wiring, and   the number of connection holes formed in an insulating film just above the first wiring is less than the number of connection holes formed in an insulating film just above a wiring of a layer lower than the first wiring.   
   
   
       27 . The semiconductor device according to  claim 25 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       28 . A semiconductor device comprising
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in different regions from each other in the deep-well; and   a field effect transistor of the second conductivity type formed in the first shallow well, wherein   a drain of the field effect transistor is connected to the second shallow well, the first shallow well is connected to a ground potential, and the gate electrode of the field effect transistor is directly or indirectly connected to the second shallow well, so that the field effect transistor is turned ON or OFF according to an amount of charges of the second shallow well.   
   
   
       29 . The semiconductor device according to  claim 28 , wherein the drain is connected to the field effect transistor and the second shallow well by using a wiring of a first layer, and the first shallow well is connected to a ground potential. 
   
   
       30 . The semiconductor device according to  claim 28  further comprising a first semiconductor region of the first conductivity type in the second shallow well, wherein the first semiconductor region is electrically connected to the gate electrode of the field effect transistor by using a second wiring. 
   
   
       31 . The semiconductor device according to  claim 28 , further comprising a first semiconductor region of the first conductivity type in the second shallow well, wherein the first semiconductor region is electrically connected to the gate electrode of the field effect transistor by using a second wiring, and the first semiconductor region is electrically connected to a ground potential using a first wiring of a layer upper than the second wiring. 
   
   
       32 . The semiconductor device according to  claim 28  further comprising a first semiconductor region of the first conductivity type in the second shallow well, wherein the first semiconductor region and the gate electrode of the field effect transistor are connected by a plug electrode buried in a connection hole formed so as to span the first semiconductor region and the gate electrode of the field effect transistor. 
   
   
       33 . The semiconductor device according to  claim 28  further comprising a capacitor element that includes: the second shallow well; an insulating film formed on the second shallow well; and a gate formed on the insulating film, wherein a gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using a second wiring. 
   
   
       34 . The semiconductor device according to  claim 28  further comprising a capacitor element that includes: the second shallow well; an insulating film formed on the second shallow well; and a gate formed on the insulating film, wherein a gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using a second wiring, wherein the gate of the capacitor element is electrically connected to a ground potential by using a first wiring of a layer upper than the second wiring. 
   
   
       35 . The semiconductor device according to  claim 28  further comprising a capacitor element that includes: the second shallow well; an insulating film formed on the second shallow well; and a gate formed on the insulating film, wherein a gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using a second wiring, wherein
 a gate capacitance of the capacitor element is larger than a gate capacitance of the field effect transistor.   
   
   
       36 . The semiconductor device according to  claim 28  further comprising a capacitor element that includes: the second shallow well; an insulating film formed on the second shallow well; and a gate formed on the insulating film, wherein a gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using a second wiring, wherein
 a capacitance obtained by connecting a gate capacitance of the capacitor element and a capacitance of a depletion layer formed in the second shallow well below the gate of the capacitor element in series is larger than a gate capacitance of the field effect transistor.   
   
   
       37 . The semiconductor device according to  claim 28  further comprising a capacitor element that includes: the second shallow well; an insulating film formed on the second shallow well; and a gate formed on the insulating film, wherein a gate of the capacitor element is electrically connected to the gate electrode of the field effect transistor by using a second wiring, wherein
 an inversion layer is formed in the second shallow well below the gate of the capacitor element, and a gate capacitance of the capacitor element is larger than a gate capacitance of the field effect transistor.   
   
   
       38 . The semiconductor device according to  claim 28  further comprising a first semiconductor region of the first conductivity type in the second shallow well, wherein the first semiconductor region is electrically connected to the gate electrode of the field effect transistor using a second wiring, and
 a junction capacitance of the first semiconductor region and the second shallow well is larger than a gate capacitance of the field effect transistor.   
   
   
       39 . A semiconductor device comprising:
 a substrate of a first conductivity type;   a deep-well of a second conductivity type different from the first conductivity type and formed in the substrate;   a first shallow well of the first conductivity type and a second shallow well of the second conductivity type formed in different regions from each other in the deep-well; and   a field effect transistor of the second conductivity type formed in the first shallow well, wherein   a drain of the field effect transistor is connected to the second shallow well, the first shallow well is connected to a ground potential, and a gate electrode of the field effect transistor is connected to a wiring put in a floating state, so that the field effect transistor is turned ON or OFF according to an intermediate potential of the wiring put in the floating state.   
   
   
       40 . The semiconductor device according to  claim 39 , wherein the drain of the field effect transistor is connected to the second shallow well by using a wiring of the first layer, and the first shallow well is connected to a ground potential. 
   
   
       41 . The semiconductor device according to  claim 39 , wherein a potential that makes the field effect transistor turned OFF is applied to the wiring put in the floating state by a wiring of an layer upper than the wiring put in the floating state. 
   
   
       42 . The semiconductor device according to  claim 39 , wherein the gate electrode of the field effect transistor is electrically connected to a ground potential by using a third wiring of a layer upper than the wiring put in the floating state. 
   
   
       43 . The semiconductor device according to  claim 31 , wherein the first wiring is a wiring of an uppermost layer. 
   
   
       44 . The semiconductor device according to  claim 30 , wherein the second wiring is a wiring of a first layer. 
   
   
       45 . The semiconductor device according to  claim 42 , wherein the third wiring is a wiring of an uppermost layer.