Closed-grid bus architecture for wafer interconnect structure

Abstract

An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

1 - 14 . (canceled) 
   
   
       15 . An apparatus for distributing test signals, said apparatus comprising:
 distributing means for distributing a test signal received from a tester for one input terminal of a device under test to a plurality of input terminals; and   isolating means for electrically isolating one of said input terminals from another of said input terminals,   wherein said isolating means comprises a thin film resistor disposed on said distributing means.   
   
   
       16 . The apparatus of  claim 15 , wherein each of said plurality of terminals to which said distributing means distributes said test signal is disposed on a different device under test. 
   
   
       17 . The apparatus of  claim 15 , wherein said distributing means comprises;
 a substrate, and   a conductive trace.   
   
   
       18 . The apparatus of  claim 17 , wherein said distributing means comprises a plurality of traces, interconnected to form a closed-grid bus. 
   
   
       19 . The apparatus of  claim 17 , wherein said isolating means further comprises a plurality of thin film resistors, each disposed between said trace and one of said input terminals. 
   
   
       20 . A method of making an apparatus for distributing test signals, said method comprising:
 providing a substrate;   disposing on said substrate a trace configured to receive a test signal;   electrically connecting a plurality of contact elements to said trace, each said contact element disposed to make an electrical connection with an input terminal of a device under test; and   disposing a plurality of thin film resistors on said substrate, each said thin film resistor disposed in an electrical path between said trace and one of said contact elements.   
   
   
       21 . The method of  claim 20 , wherein said contact elements connected to said trace are disposed to contact input terminals on different devices under test. 
   
   
       22 . The method of  claim 20  further comprising:
 disposing a plurality of traces on said substrate, each said trace configured to receive a test signal; and   electrically connecting a set of contact elements to each said trace, wherein each set of contact elements is disposed to contact input terminals on a plurality of devices under test.   
   
   
       23 . The method of  claim 20 , wherein said trace comprises a plurality of sub-traces configured to form a closed-grid bus. 
   
   
       24 . The method of  claim 20 , wherein each said contact element comprises a probe. 
   
   
       25 . The method of  claim 24 , wherein said probe comprises a spring contact. 
   
   
       26 . The method of  claim 20 , wherein each said input terminal of a device under test comprises a spring contact, and each said contact element connected to said trace comprises a pad. 
   
   
       27 . The method of  claim 20 , wherein at least one of said trace or said thin film resistors are disposed within said substrate. 
   
   
       28 . The method of  claim 27 , wherein:
 said substrate is a multilayer substrate, and   said at least one of said trace or said thin film resistors are disposed on an inner layer of said substrate.