Semiconductor packages and methods of manufacturing the same

Abstract

Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

1 . A semiconductor package, comprising:
 a substrate including a chip pad;   a redistributed line which is electrically connected to the chip pad and includes an opening and an external terminal connection portion; and   a first external terminal connection pad which is disposed at the opening and electrically connected to the redistributed line.   
   
   
       2 . The semiconductor package of  claim 1 , wherein the redistributed line is divided into a first redistributed line and a second redistributed line by the opening and the second redistributed line is connected to the first redistributed line. 
   
   
       3 . The semiconductor package of  claim 1 , wherein the redistributed line is divided into a first redistributed line and a second redistributed line by the opening and the second redistributed line is spaced apart from the first redistributed line. 
   
   
       4 . The semiconductor package of  claim 3 , wherein the first external terminal connection pad is disposed between the first redistributed line and the second redistributed line. 
   
   
       5 . The semiconductor package of  claim 4 , further comprising:
 a first barrier layer which is disposed between the first external terminal connection pad and the redistributed line to prevent an ingredient included in the redistributed line from being diffused into the first external connection pad.   
   
   
       6 . The semiconductor package of  claim 4 , further comprising:
 a second external terminal connection pad which is disposed on the redistributed line and electrically connected to the redistributed line.   
   
   
       7 . The semiconductor package of  claim 6 , further comprising:
 a second barrier layer which is disposed between the second external terminal connection pad and the redistributed line to prevent an ingredient included in the redistributed line from being diffused into the second external connection pad.   
   
   
       8 . The semiconductor package of  claim 6 , wherein a lowest bottom surface of the first external terminal connection pad is at the same level with a lowest bottom surface of the second external terminal connection pad. 
   
   
       9 . The semiconductor package of  claim 1 , further comprising:
 one of a solder bump electrically connected to the first external terminal connection pad and a bonding wire electrically connected to the external terminal connection portion.   
   
   
       10 . The semiconductor package of  claim 1 , further comprising:
 a passivation layer which is disposed on the substrate and exposes a portion of the chip pad so that the redistributed line provides a path connected to the chip pad; and   an insulating layer which is disposed on the passivation layer and exposes a portion of the redistributed line so that a portion of the redistributed line is used as the external terminal connection portion.   
   
   
       11 . A semiconductor package, comprising:
 a first semiconductor package that includes a redistributed line including an external terminal connection portion that is disposed on a first chip;   a bump pad electrically connected to the redistributed line, the bump pad to which a solder bump being connected, and a bonding wire connected to the external terminal connection portion;   a second semiconductor package including a second chip electrically connected to the first semiconductor package in a flip chip type by the medium of the solder bump; and   a printed circuit board electrically connected to the first semiconductor package by the medium of the bonding wire.   
   
   
       12 . The of semiconductor package  claim 11 , wherein one of the first and second chips is a memory chip and the other is a logic chip. 
   
   
       13 . The semiconductor package of  claim 11 , wherein the first semiconductor package further comprises a barrier layer which is disposed between the bump pad and the redistributed line to prevent an ingredient included in the redistributed line from being diffused into the bump pad. 
   
   
       14 - 20 . (canceled) 
   
   
       21 . The semiconductor package of  claim 1 , comprising:
 a barrier layer disposed between the redistributed line and the first external terminal connection pad; and   an insulating layer in contact with the redistributed line and the first external terminal, but not in contact with the barrier layer.   
   
   
       22 . A semiconductor package, comprising:
 a first semiconductor package that includes a plurality of redistributed lines including recessed portions and non-recessed portions;   bump pads disposed above the recessed portions and non-recessed portions; and   solder bumps connected only to the bump pads disposed over the non-recessed portions of the redistributed lines.   
   
   
       23 . A semiconductor package, comprising:
 a substrate including a chip pad;   a redistributed line electrically connected to the chip pad and including an opening that divides a first redistributed line from a second redistributed line;   a passivation layer disposed on the substrate,   wherein thicknesses of the first and second redistributed lines are equal to a thickness of the passivation layer.   
   
   
       24 . (canceled)