Method of trimming a hard mask layer, method for fabricating a gate in a mos transistor, and a stack for fabricating a gate in a mos transistor

Abstract

A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.

1 . A stack structure for forming a gate of a MOS transistor, comprising:
 a substrate comprising a plurality of shallow trench isolations therein;   a dielectric layer, a conductive layer and a hard mask layer formed on said substrate in sequence;   a multi-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on said hard mask layer, wherein said silicon-containing photo resist layer comprises 10-30% silicon and said hard mask layer has a high etching selectivity ratio to said conductive layer.   
   
   
       2 . The stack structure of  claim 1  wherein said substrate comprises single crystal Si and silicon on insulator (SOI). 
   
   
       3 . The stack structure of  claim 1  wherein said bottom anti-reflective coating comprises a 365 nm photo resist layer. 
   
   
       4 . The stack structure of  claim 1  wherein said hard mask layer is an oxide layer. 
   
   
       5 . The stack structure of  claim 4  wherein said hard mask layer comprises SiON, SixNy, SiO 2 , TEOS or a combination thereof.