Flash memory device and flash memory system including the same

Abstract

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

1 . A flash memory device comprising:
 a memory cell array;   a signal generator receiving a first data fetch signal and outputting a second data fetch signal; and   an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal,   wherein the second data fetch signal is output along with data output from the output buffer circuit.   
   
   
       2 . The flash memory device of  claim 1 , wherein the signal generator delays the first data fetch signal and outputs the delayed first data fetch signal as the second data fetch signal. 
   
   
       3 . The flash memory device of  claim 1 , further comprising: an input buffer circuit configured to input data in sync with the first data fetch circuit. 
   
   
       4 . The flash memory device of  claim 1 , further comprising:
 a control logic circuit; and   a reading/programming circuit controlled by the control logic circuit, reading data from the memory cell array in a reading operation and programming data into the memory cell array in a programming operation.   
   
   
       5 . The flash memory device of  claim 4 , wherein the control logic circuit activates the signal generator to output the second data fetch signal in a data output cycle. 
   
   
       6 . The flash memory device of  claim 1 , further comprising: a control logic circuit configured to discriminate a data input/output cycle into one of an address latch cycle, a command latch cycle, an input data latch cycle, and a data output cycle with reference to a combination of an address latch enabling signal and a command latch enabling signal. 
   
   
       7 . The flash memory device of  claim 6 , wherein the first data fetch signal is toggled in the address latch cycle, the command latch cycle, the input data latch cycle, and the data output cycle. 
   
   
       8 . The flash memory device of  claim 6 , wherein the control logic circuit determines the data input/output cycle as a serial access cycle if the address and command latch enabling signals are both set on a high level. 
   
   
       9 . The flash memory device of  claim 1 , wherein a single data rate mode is set as a default mode. 
   
   
       10 . The flash memory device of  claim 9 , wherein an identification reading operation is conducted in the single data rate mode. 
   
   
       11 . The flash memory device of  claim 10 , wherein the default mode is selectively changed by a selection signal or command after the identification reading operation. 
   
   
       12 . A flash memory device comprising:
 a memory cell array;   a control logic circuit configured to discriminate a data input/output cycle into one of an address latch cycle, a command latch cycle, an input data latch cycle, and a data output cycle with reference to a combination of an address latch enabling signal and a command latch enabling signal;   a reading/programming circuit controlled by the control logic circuit, reading data from the memory cell array in a reading operation and programming data into the memory cell array in a programming operation;   a signal generator delaying a first data fetch signal and outputting a second data fetch signal if the data input/output cycle is determined as the data output cycle; and   an output buffer circuit sequentially outputting data of the reading/programming circuit in sync with rising and falling edges of the second data fetch signal if the data input/output cycle is determined as the data output cycle,   wherein the second data fetch signal is output externally along with data output from the output buffer circuit.   
   
   
       13 . The flash memory device of  claim 12 , further comprising: an input buffer circuit operating in sync with the first data fetch signal and interfacing data to be stored in the memory cell array. 
   
   
       14 . The flash memory device of  claim 12 , wherein the output buffer circuit is configured to interface data in sync with the second data fetch signal by an edge alignment mode and a double data rate mode 
   
   
       15 . A flash memory system comprising:
 a flash memory device; and   a memory controller configured to control the flash memory device,   wherein the flash memory device generates a second data fetch signal from a first data fetch signal provided from the memory controller in a reading operation and outputs read data to the memory controller in sync with the second data fetch signal, wherein the second data fetch signal is transferred to the memory controller along with the read data.   
   
   
       16 . The flash memory system of  claim 15 , wherein the flash memory device outputs data to the memory controller in sync with the second data fetch signal by an edge alignment mode and a double data rate mode. 
   
   
       17 . The flash memory system of  claim 15 , which includes one of solid state drive (SSD), a memory module, and a memory card. 
   
   
       18 . The flash memory system of  claim 15 , wherein the flash memory device is configured to discriminate a data input/output cycle into one of an address latch cycle, a command latch cycle, an input data latch cycle, and a data output cycle with reference to a combination of an address latch enabling signal and a command latch enabling signal which are provided from the memory controller. 
   
   
       19 . The flash memory system of  claim 18 , wherein the flash memory device determines the data input/output cycle as a data output cycle if the address and command latch enabling signals are all set on high level. 
   
   
       20 . The flash memory system of  claim 18 , wherein the data output cycles includes a serial access cycle of a reading operation, a data output cycle of an identification reading operation, and a data output cycle of a state reading operation.